problems about dual-rank DDR3 mode in TCI6618

Hi all,

***********************************************************************************************

We had designed a board based on TCI6618. In our board, the DDR3 controller connects with 4 2Gb(16MB*16*8) DDR3 RAM chips.

***********************************************************************************************

In the PCB, the CLK1p/n&CKE1p/n&CE1 connnects with Byte Lane 0, 1, 2, 3.

And the CLK0p/n&CKE0p/n&CE0 connects with Byte Lane 5, 6, 7, 8.

And the DDR3 runs at 1333MT/s.

***********************************************************************************************

With this topology, I used the GEL file of C6670's EVM. And modified these regs' values below

TEMP |= 0x0 << 14; // NM bit field 15:14------------------set 64-bit width

TEMP |= 0x5 << 7; // ROWSIZE bit field 9:7--------------set ROWSIZE=14 bits

TEMP |= 0x1 << 3; // EBANK bit field 3:3------------------set using CE0&CE1

DDR_SDCFG = TEMP;

***********************************************************************************************

After these settings, I test the DDR3's writing and reading.
And I got errors!!

***********************************************************************************************

But if I TEMP |= 0x0 << 3; // EBANK bit field 3:3------------------set only using CE0

I tried to write the DDR3, it shows me that only half DDR3 space(the high 32 bits) works well.

***********************************************************************************************

So can anyone help me to make all the DDR3 chips wok well?