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About DDR3 2 ranks usage of TMS320C6678

Jason Gao
Intellectual 720 points

Hi Sir:

I see in document SPRABL1A (DDR3 Design Requirements for KeyStone Devices Application Report) page 72,

CS1# is described in table 40 as  "Leave unconnected" for two rank design, is it right?

what is more, we have a design based on C6678 and we want to achieve most as large DDR3 storage capacity  as possible,

and 2 ranks design should be used.  I think we should use 16 pieces of  X8 DDR3 device should be used, is it right?

The 8 pieces in rank0 is the same with the 8 pieces in rank1 in pin connection except for the first 8 pieces connected to

CS0# and the other 8 connected to CS1#,  is it right? 

Thank you very much.

  • 0
    TI__Mastermind 42545 points

    You are correct that CS1# would be connected to eight of your devices in a dual rank design.  The error in the table on page 72 will be corrected in the next release.  Please be sure to follow all the routing guidelines carefully.  Dual rank systems are difficult to route due to the stub length requirements.  Also note that the address mirroring used on some DIMMs to shorten stubs on the address lines is not supported by the C6678. 

  • 0 in reply to Bill Taboada
    Intellectual 720 points

    Thank you Bill.

    Does C6678 support RDIMM usage? Only UDIMM is mensioned in C6678 DDR3 design documentation.

  • 0 in reply to Bill Taboada
    Prodigy 130 points

    Hi Sir

        We have a problem，Our customers need 8G memory for C6678，we use 10 pieces (contain ECC)of  MT41K512M16HA-125 IT and fly-by for layout,

    Five pieces SDRAM on top,Five pieces SDRAM on bot,dual rank，Can this be designed？

        we found，memory will go wrong t when the CS0 、CS1 is turned on by software, But when  turn off the CS1, the memory will not go wrong，

    How do we solve this problem？thanks！

  • 0 in reply to bing zhou
    TI__Mastermind 42545 points
    Hi,
    Implementing 8G of memory with a set of memories on both the top and bottom of the board is almost impossible with the routing restriction for the C6678. Since the device does not support address mirroring, the stubs on the address lines are usually longer then recommended. In addition, we only support a single set of delay numbers during the leveling process. The difference in address trace lengths between the ranks will cause instability when operating at full speed.
    If 8G of memory is needed we recommend using twin-die memory components. This will allow you to achieve 8G with five x16bit or nine x8bit devices. Since the two ranks are implemented inside the memory device, the length of address lines will be identical and address mirroring is not needed.
    Regards,
    Bill
  • 0 in reply to Bill Taboada
    Prodigy 130 points
    Hi Bill
    There are 4 combination for DDRSLRATE[1:0],(fastest,fast,low,lowest)
    Our C6678 DDR3 can be stable in 1066MTS with 8G dual rank(MT41K512M16HA-125 IT) and setting fast parameters，
    We'll do some more experiments，i want to know How many differences in memory actually read and write speed with different parameters（fastest,fast,low,lowest），thanks！
  • 0 in reply to bing zhou
    TI__Mastermind 46460 points

    This should have been set up as a totally new thread with a proper title.  That way others can search for the feedback.  Please start a new thread and we will respond to it.

    BTW, I am sure this is answered already in another forum post.

    Tom

  • 0 in reply to Bill Taboada
    Prodigy 20 points
    Hi Bill,
    The twin-die DDR3 SDRAM configurition has been virefied?

    Tom Johnson said planing to test the twin-die configurition, but I do not know about the result.
    post as below:
    e2e.ti.com/.../317347

    best regards
  • 0 in reply to Jason Chen11
    TI__Mastermind 46460 points

    The KeyStone I DDR3 Initialization Application Report (SPRABL2D) was revised in January of 2015.  It now contains instructions for configuring the Controller and PHY to support twin-die SDRAMs.  This was not validated on any TI reference design but we provided this guidance as a service to customers eager to try it.  Based on feedback from those who implemented this, we believe that this configuration is valid.  However, we do not have confirmation that this was ever implemented on a board that went to production.  There were reports that some boards that implemented twin-die devices had layout issues resulting in occasional errors.  More recently monolithic 8Gb DDR3 SDRAM devices became affordable and we have not seen interest in twin-die use since then.  As stated previously, we believe that the guidance provided is sufficient for success but we cannot guarantee it since we did not characterize it on a TI reference platform.  Therefore, our current recommendation is to implement DDR3 SDRAM topologies using monolithic (single-die) SDRAMs.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 20 points
    Tom,
    Thanks for your timely reply. May be we should use 8Gb monolithic SDRAM.