[FAQ] AM625/AM623 Custom board hardware design – Power sequencing between SOC (Processor) and the Attached devices (Fail-safe)

Hi Board designers, 

Refer below inputs for the Power sequencing between SOC (Processor) and the Attached devices related queries

1. Can I power the SOC (Processor) IOs and Attached devices from different power sources?

Most of the processor IOs are not fail-safe. Refer the data-sheet for information on available fail-safe IOs.  The Power supply is required to be ramped and stable before the SOC (Processor) IOs are driven by external inputs.

2. Is there a recommended power sequencing requirement to be followed between the SOC (Processor) and the attached devices?

It is recommended to power the IOs of the external device from the same power source as the respective SOC (Processor) IOs to ensure the system never applies potential to an IO that is not powered. This is needed to protect the IOs of either device.  

The core supply for the attached devices can be applied from an independent power source.

3. I have a modular design. I have the attached devices on the carrier board and the SOC (Processor) on the SOM board. Any power sequencing recommendations?

There are 2 possible options - the board designer needs to route the IO power rails from the SOM generated power supplies to the base board to power attached devices, or place the PMIC on the base board and route all of the supplies to the SOM

4. Is there a recommendation to be followed when the SOC (Processor) and the attached devices are powered from different sources?

The interface signals between the SOC (Processor) and the attached device that could be driven to a voltage level outside of the recommended operating voltage, needs to be isolated using FET switches or FET BUS switches.

FET bus switches have been used in the Starter Kit design for other applications but these devices could be used for signal isolation. The FET bus switches are recommended to be enabled by an ANDing logic. The Power good output from the power sources of the SOC (Processor) and the attached device are the inputs to the FET bus switch

5. Are these recommendations applicable for all the Sitara family of devices?

This is applicable for AM335x, AM64x, AM437x, AM62x, AM62Ax, AM62Px

      6. Examples of failsafe IOs

Refer below summary of fail-safe IOs for AM625 

Refer below section of the data sheet

Specifications
Absolute Maximum Ratings

Additional notes from the AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 / AM62A7 / AM62A3 Schematic Design and Review Checklist

Signal Isolation for Fail-Safe Operation

In case the processor and the attached devices or an additional host are powered by different power sources, signal isolation is recommended since most of the processor IOs are not fail-safe. It is recommended to route the signals through a FET bus switch circuit designed to automatically isolate the two devices anytime the IO power is not valid for both devices. The FET bus switch and control logic are recommended to be powered from an always on power supply and only enabled by an AND function of power good signals from different power sources.

 Attached device 

An attached device includes any device that is interfaced to the SoC (Similar SoC, Different SoC, MCU, Memory, Interface devices or any external devices that sends or receives data).

Regards,

Sreenivasa