Hi Board designers, 

Here are some of the commonly observed errors for OSPI/QSPI MEMORY Interface during Custom board hardware design

1. Series resistor for the OSPI_CLKOUT 

A 0R series resistor is recommended as an option for tuning during functional and performance testing 

SoC Data Sheet reference 

OSPI/QSPI/SPI Board Design and Layout Guidelines

2. Parallel pulls for OSPI Data, Clock and control signals

The Pull are for attached device. Verify the attached device data sheet for availability of internal pulls.

Most of the SoC IOs will be off by default , so any attached device inputs that are sourced from the processor will be floating without external pull, until the device boots and software initializes the IOs. Parallel pulls are recommended for OSPI interface signals. 

Refer SK schematics for implementation.

3. ANDing logic for OSPI reset 

The ANDing logic provides flexibility to reset the attached memory device. Refer SK schematics for implementation.
RESETSTATz output will satisfy the power-on and warm reset functions and can be used to reset the attached device. Ensure IO level compatibility between the RESETSTATz output and the attached device reset input. You will need a two input AND gate to insert the software controlled GPIO reset function for the case where software needs to initiate a reset to only
A pullup and an isolation resistor is recommended for the SoC IO output connected to the ANDing logic near to the AND gate.
When ANDing logic is not used, verify the IO compatibility of the SoC reset status output used and the attached memory device.

4. OSPI clock loopback 

Place Series resistor 0R close to the LBCLKO pin near to the processor

TRM reference 

Octal Serial Peripheral Interface (OSPI)

Data Sheet reference 

OSPI/QSPI/SPI Board Design and Layout Guidelines

5. DQS pulldown  not provided  near to Processor

Add a 1K or Similar pulldown. Refer SK schematics.

TRM Reference (AM62P)

12.4.2.4.2.1.4 External Pull Down on DQS
Per the OSPI protocol, the FLASH device drives DQS while CS is asserted. When CS is not asserted the FLASH device presents HiZ on DQS. When configured to use DQS, the controller uses the DQS as a clock, which samples the incoming data into a FIFO. Noise on the DQS when it is HiZ can cause spurious false triggering of the FIFO and filling it with invalid data. There is no way to clear this data except to reset the OSPI module.
To avoid this issue, it is recommended to add a pull down on the DQS line. During device wakeup, before the IO ring is configured properly, the CS to the FLASH device is HiZ. Depending on the actual level of the CS line the FLASH device might drive the DQS High, Low or HiZ. A pull down on DQS forces the DQS input to Low, but the DQS might still be High or in the presence of noise there might be transitions between Low and High. This again can cause the same issue of capturing garbage data in the Controller FIFO.
To avoid this issue it is recommended to release the OSPI from reset only after the IO ring is configured properly.

6. What is the default drive strength and can the drive strength be controlled?

These are typically about 40 ohms, but the customer should be using the IBIS model to determine the drive strength of the pins. 
The drive strength must remain in the default state since this is the only condition used during timing closure of the peripherals.

Note: These recommendations are applicable for AM64x family of processors.

Reference Links 

(12) SK-AM62A-LP: pull up registers for OSPI flash - Processors forum - Processors - TI E2E support forums

(12) SK-AM62A-LP: The background of DNI of pull up registers for OSPI flash - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa