[FAQ] AM625 / AM623 / AM62A / AM62P / AM64x / AM243x Design Recommendations / Commonly Observed Errors during Custom board hardware design – DDR4 / LPDDR4 MEMORY Interface

Hi Board designers, 

Here are some of the commonly observed errors and recommendations for DDR4 / LPDDR4 MEMORY Interface during Custom board hardware design.

Recommendations 

1. DDR design guide 

AM62x

https://www.ti.com/lit/an/sprad06/sprad06.pdf

AM62Ax and AM62Px

https://www.ti.com/lit/an/sprad66a/sprad66a.pdf

2. Supported Memory Size, Speed and Type,

Refer to the processor specific data sheet.

AM62x

https://www.ti.com/lit/gpn/am625

AM62Ax

https://www.ti.com/lit/gpn/am62a7

AM62Px

https://www.ti.com/lit/gpn/am62p

Reference Links 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1278830/am625-am625-8bit-single-rank-ddr4-chip-x-2pcs-support

3. DDR4 Bit swapping and Prime bit swapping restrictions

For DDR4, DQx swizzling is allowed (no register config changes are necessary).  No swizzling of DM, DQS, or address is allowed.

The restriction on prime bit swapping (D0 and D8)  on DDR4 is not required for any of the AM6x processor family.

4.Customer is looking for design guidance with DDR4 and not have external VTT termination  Is it possible to do that?

 AM62x and AM64x with DDR4 can be designed with no VTT termination as long as all signals are point to point with one load (ie, design uses one DDR4 device).

The AM62x SK is an example of this.

https://www.ti.com/tool/SK-AM62B-P1

In case you would want to add terminations follow the AM64x EVM 

https://www.ti.com/tool/TMDS64EVM

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1161417/am623-vtt-regulation-and-decoupling

5. Is there some recommendations for DDR4 differential clock terminations

it is recommended to follow the device specific EVM or SK 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1231613/am625-ddr-clk-termination-specification/4665907?tisearch=e2e-sitesearch&keymatch=AM625%2520ddr4%2520spread%2520spectrum#4665907

6.The SK-AM62B-P1 design uses a single 2GB DDR4chip. The customer now requires  4GB and 8GB . Any suggestions?

We do not support multiple loads on the DDR4 data bus, so customer would have to accomplish this with a larger density memory device.  We  support up to 2 x8 DDR4 devices such that each data byte has one load. For higher density you can connect 2 x8 devices in a dual rank configuration.

Verify the BG0 and BG1, CS0 and CS1 connection and ensure these are connected as per the recommendations based on the selected memory and density.

7. LPDDR4 Bit swapping for AM62A and AM62P

Refer Channel, Byte, and Bit Swapping section of AM62Ax/AM62Px LPDDR4 Board Design and Layout Guidelines

8. LPDDR4 Bit swapping for AM62X

AM62x will follow AM62A/P for LPDDR4, DQx/DM can be swizzled within a byte, and bytes can be swapped

Refer Channel, Byte, and Bit Swapping section of AM62Ax/AM62Px LPDDR4 Board Design and Layout Guidelines

AM62x DDR Board Design and Layout Guidelines will be updated.

9. I plan to use TPS51200 for DDR4 and have some confusion about the REFOUT pins of the TPS51200. I found that some EVB designs use the output of REFOUT as DDR4 VREFCA, and some other EVB designs use resistor divider.
So, I wonder which way is better?

Either REFOUT or resistor divider can be used for DDR4 VREFCA.  Use of Resistor Divider and filters  can be avoided when REFOUT is available.

10.  Do you have any recommendation for the Resistor Divider implementation

Refer below E2E:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1318631/am62x-sk-board-ddr_vrefca-circuit

11. SK-AM64B: AM64x DDRSS memory capacity range question 

Refer the below E2E:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1246819/sk-am64b-sk-am64b-ddrss-memory-capacity-range-question

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1246278/sk-am64b-ddrss-memory-capacity-range-question

Regards,

Sreenivasa

Regards,

Sreenivasa