[FAQ] AM625 / AM623 / AM620-Q1 / AM62L / AM64x/ AM243x (ALV) / AM62Ax / AM62D-Q1 / AM62Px Design Recommendations / Commonly Observed Errors during Custom board hardware design – eMMC MEMORY Interface

Hi Board designers, 

Refer below inputs:

1. Pullup recommendation 

The Pullup recommendations depend on the eMMC PHY implementation 

AM62x, AM62L, AM62Ax and Am62D-Q1 implement soft PHY

In soft PHY implementation, the MMC0 pins have alternate functions that can be configured.

Connect external pullup resistor for the data line (MMC0_DAT0) (close to eMMC device).
eMMC device (as long as the eMMC device is compliant to the eMMC standard) has the pullups enabled for data signals
D7..D1 by default. The eMMC device will turn off its D3..D1 pulls when entering 4-bit mode and D7..D1 pulls when entering 8-bit mode.
The eMMC host software should turn on the respective DAT pulls when it changes the mode.

(+) [FAQ] AM62A7: MMC0 Pull Resistor Requirements - Processors forum - Processors - TI E2E support forums

This e2e exchange: AM6442: eMMC pull-ups necessary or not?, results in a statement that the AM6442 requires no external pull resistors on the MMC0 interface, and that the processor will provide all required pull levels.  Is this also the case for the AM62A processors?

No. You must connect an external pull-down on CLK, and external pull-ups on CMD and DAT0 to prevent these eMMC device inputs from floating until software initializes the host controller and AM62Ax IOs associated with MMC0. The eMMC standard requires an eMMC device to have internal pulls turned on by default on DAT[7:1], so these signals do not require an external pull-up resistor. Software should turn on the respective internal AM62Ax DAT pull-ups when the bus width is increased from 1-bit mode to 4-bit or 8-bit mode.

This is required on AM62A because the IOs associated with MMC0 are implemented with standard dual-voltage LVCMOS IO cells with the capability of multiplexing additional signal functions to the respective device pins. Therefore, these MMC0 IOs are turned off by default since it is unknow what may be connected to these pins. That is not the case for AM64x since it's the MMC0 port is dedicated to eMMC.

The AM62x IOs used for MMC0 will power-up in the off state until software configures them. eMMC devices are required to have internal pull-up resistors on DAT[7:1], but they are not required to have internal pull resistors on CLK, CMD, and DAT0. External pull resistors are recommended for CLK, CMD, and DAT0 to prevent floating inputs on the memory device while waiting for software to configure the AM62x IOs.

(+) [FAQ] AM62: Power sequence of VDDSHV_MMCx - Processors forum - Processors - TI E2E support forums

The on-board eMMC device is connected to MMC0 and the IOs associated with this port are powered by VDDSHV4. The on-board eMMC device does not need to change voltage dynamically, so VDDSHV4 is connected to a fixed 3.3V or 1.8V supply. Typically on-board eMMC devices are operated at 1.8V.

The SD Card is connected to MMC1 and the IOs associated with CMD, CLK, and DAT[3:0] are powered by VDDSHV5. These are the IOs that must change their operating voltage dynamically. So the VDDSHV5 power source must default to 3.3V and change to 1.8V when software is ready to change the IO voltage. The IOs associated with SDCD and SDWP are powered by VDDSHV0. These signals only connect to mechanical switches in the SD Card socket and should be pulled high with external pull-up resistors connected to VDDSHV0.  VDDSHV0 can be 3.3V or 1.8V and is not expected to change voltage.

The SD Card is powered by a fixed 3.3V source and it has a similar internal power supply circuit that changes its IO supply from 3.3V to 1.8V when software sends a command telling the card to change voltage.

There must be a software switchable 3.3V power source that provides power to the SD Card and the VDDSHV5 power source. The 3.3V power switch is required to cycle power to the SD Card and the VDDSHV5 power rail at the same time anytime the SD Card needs to be reset. Cycling power to the SD Card is the only way it can be reset since there is no reset signal on SD Cards. Without this power switch you would need to cycle power to the entire system to reset the SD Card. The SD Card must be reset anytime it has previously operating at 1.8V and needs to return to 3.3V mode. One good example where you may encounter this problem is when the watchdog timer expires and causes the processor to reset, which will return its VDDSHV5 IO voltage to 3.3V  and the SD Card will still be in 1.8V mode because power didn't cycle. This is a requirement defined in the SD Card specification.

AM62Px / AM64x / AM243x (ALV) implements a hard PHY

In hard PHY implementation, the MMCO pins have dedicate eMMC functionality. When not used, it is recommended to connect these pins as per the pin connectivity recommendations of the specific device data sheet.

No external pull resistors are required for MMC0 since the PHY includes and dynamically controls the internal pull resistors as required for an eMMC.
Pullups for D7..D0 and CMD are internally enabled during reset and after reset by the processor eMMC PHY.
Pulldown is enabled for the DS pin and the clock output is driven low during reset and by the SS (The subsystem selected with MUXMODE determines the output buffer state) after reset.
There are no PADCONFIG registers associated with the MMC0 pins.
The internal pulls associated with the MMC0 pins are dynamically controlled by the MMC0 host and PHY.
Provision for External pulls are not a requirement for the eMMC data, CMD, DS and the CLK signals.

2. Power supply and Sequencing 

The recommendation is to power the processor IO supply rail and the eMMC device from the same power source

3. Series resistor for eMMC clock output from the processor

it is  a good idea to place a series termination resistor as close as possible to the MMC0_CLK pin in case it is needed to dampen reflections caused by an impedance mismatch.

Peripheral Clock Output Series Resistor
Series resistor on the clock output near to the processor clock output (MCSPI, MCASP) pins are recommended for control of possible reflections  (signal distortion) at the source of the clock output since the clock is also being used for retiming.
For MMC0, MMC1, MMC2, OSPI0, GPMC0 interfaces, an unbonded pad is used (internal) for retiming. We do not use the same clock that is sent across the PCB to the attached device for our capture clock. We branch the output clock into two paths inside the device, where the clock is sent to two separate IO cells. One IO cell is connected to a package ball, which is used to source a clock to the attached device. The other IO cell is unbounded (not connected to any package ball). The clock we use as the receive capture clock is sent out through the unbounded IO cell and looped back into the device before being used as the capture clock. We do this so the clock has the same delay that is inserted on the clock going out to the attached device and the same delay that is inserted on the data coming back in from the attached device. The unbonded IO cell pad never experiences the voltage step that is produced on the source end of a PCB signal trace. A low value series resistor (0Ω to start) is recommended (provisioned) for control of possible signal reflections (signal integrity purpose).

4.Series resistors for Data and command signals 

This is not a requirement. Optionally the series resistors can be included to  improve signal integrity and custom board design/layout dependent.

5. Calibration resistor 

Refer to the device specific data sheet for the recommendations including the resistor value.

6. Alternate Part recommendations

TI doesn't make specific component recommendations.
From the hardware perspective the MMC0 port on the AM6 devices are  compatible with the eMMC standards. So there should not be any hardware issue operating with any eMMC compliant device. See the MMC0 timing section of the datasheet for the eMMC data transfer modes supported.

7. Are these recommendations valid for AM64x

AM64X implements hard PHY similar to AM62P. AM62P and the general queries 2..6 can be followed.

8. Is the  reset ANDing logic for the device required and any recommendations?

The ANDing logic provides flexibility to reset the attached memory device. Refer SK schematics for implementation.
RESETSTATz output will satisfy the power-on and warm reset functions and can be used to reset the attached device. Ensure IO level compatibility between the RESETSTATz output and the attached device reset input. You will need a two input AND gate to insert the software controlled GPIO reset function for the case where software needs to initiate a reset to only
A pullup and an isolation resistor is recommended for the SoC IO output connected to the ANDing logic near to the AND gate.
When ANDing logic is not used, verify the IO compatibility of the SoC reset status output used and the attached memory device.

9. What is the default drive strength and can the drive strength be controlled?

These are typically about 40 ohms, but the customer should be using the IBIS model to determine the drive strength of the pins. 
The drive strength must remain in the default state since this is the only condition used during timing closure of the peripherals.

(+) [FAQ] AM62A7-Q1: SDIO driver strength change - Processors forum - Processors - TI E2E support forums

Drive strength is a function of changing the source impedance of an output buffer, where a lower source impedance results in a higher drive and a higher source impedance results in a lower drive. I would prefer to say we are changing source impedance rather than drive strength since this is what actually happens in the IO cell.

(+) [FAQ] AM62A7-Q1: SDIO driver strength change - Processors forum - Processors - TI E2E support forums

The AM62A7 eMMC port was timing closed with the default drive strength. Therefore, we do not recommend changing the drive strength since this could introducing signal timing issues with the attached eMMC device

We already know that; We will only try to change the drive strength. Please help share how to change?

Currently, there are no plans to support drive strength changes on the AM62Ax device.

Are there any suggestions to solve the problem of EMC-RE exceeding the standard caused by EMMC CLOCK?

You should investigate your PCB layout to determine why this signal is radiating. This typically occurs when there is a PCB trace impedance discontinuity, which also introduces signal distortion.
What does Sdhccore mean? How to understand?
This appears to be a reference to the MMCSD host controller, where it has the capability of changing the drive strength of output buffer to be one of the values defined in the eMMC standard. The output buffers being used to implement the AM62Ax eMMC port does not support all of the drive strengths defined in the eMMC standard. Therefore, the host controller drive strength control function is not implemented. The registers are there, but they have no impact on drive strength. The output buffer drive strength is fixed to 40 ohms.

Regards,

Sreenivasa

Hi Board designers, 

Refer below FAQs:

Rise/Fall Time Requirement of MMC_CLK

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1483440/am623-rise-fall-time-requirement-of-mmc_clk/5696702

Hi Board designers, 

Refer below explanation regrading eMMC interface

The AM62x IOs associated with the MMC0 port will be turned off until software initializes them. This means any signals without internal pulls will be floating until software boots and initializes the IOs. The eMMC standard requires the eMMC device to have internal pulls on the DAT[7:1] pins, but the other pins do not have internal pulls. We recommend external pull-ups on the CMD and DAT0 signals and an external pull-down on the CLK signal. The eMMC standard also says 10k pull-ups are the min value, so we do not recommend using a 10k resistor because it may be less than 10k. We typically recommend using 47k resistors to minimize loading on the signals since the pulls are only used to hold the signals in a valid logic state when not driven. Therefore, I suggest changing the value of your pull resistors and installing the pullup for CMD.  I do not expect these changes to have any effect on the issue you are seeing, but these changes should be made to ensure long-term device reliability.

Question I notice the clock rise/fall time is not very fast probably due to the 33ohm series resistor.  Does it make sense to ask them to try reducing this value?

I would not expect it to help because the setup and hold times already have margin. It may improve the clock rise/fall time, but there is good chance the signal will have more distortion due to reflections. They can try it to see what happens.

(+) AM625: AM625 schematic checklist on MMC interface - Processors forum - Processors - TI E2E support forums

The pull-down is only needed to hold the CLK input of the attached device in a valid logic state until software initializes the MMC0 host subsystem and the associated IOs. A 10k pull-down resistor should be a good choice for this use case.

Note: Most of the AM62x IOs are turned off by default to prevent any potential conflict with attached devices. This is done because these IOs support multiple signal functions via pin multiplexing and TI doesn't know what will be connected to multiplexed pins. External pulls may be required to hold inputs of any attached device in a valid logic state until software initializes the respective IOs. The CLK case described above is a good example, where an external pull should be used to protect the attached device from a floating input.

The series termination resistor value of 22 ohms was accidently carried over from another document that represented a different IO cell design, which had a lower source impedance. The 22 ohms series resistance helped match the output buffer source impedance to the PCB trace impedance. The source impedance of the IO cell implemented in AM62x is higher, so there is a good chance the series resistor is not needed. However, we encourage customers the keep the series resistor just in case their PCB design needs some additional series resistance to eliminate reflections due to impedance mismatch.

Regards,

Sreenivasa

Hi Board designers, 

Refer information related to eMMC clock:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1466492/faq-am625-is-the-emmc-clocks-maintained-when-read-and-write-operations-are-finished

I would like to know if the AM6352 continuously maintains the eMMC clock or if it stops it when it finishes the read and write processes.

Why asking ?
In most eMMC the “patrol” that refreshes and monitors the health of the memory works when it has the clock running.

If so, I was able to confirm the MMCSD host controller implemented in AM62x devices has the capability to pause the clock when there are no transfers, but that function is turned off by default.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1298166/am623-emmc-clock-output/4929951

The eMMC standard allows the host to stop the clock during read operations. The host controller implemented in AM62x uses this feature when the internal buffer is full. In these circumstances, the host controller will stop the clock in order to avoid buffer overrun condition.

Regards,

Sreenivasa

Hi Board designers, 

Additional references:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1089730/am4378-intermediate-potential/4041586

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1090498/am4378-intermediate-potential-during-reset

e2e.ti.com/.../2505155

Your first question cannot be answered without including actual PCB delays in any peripheral timing analysis.

There may be cases where a resistor/capacitor network can be used to delay a signal and help with timing, but this approach can be problematic. Inserting additional signal trace on the PCB to adjust timing may be a better approach. 

Timing requirements are given to the SOC design team and they make internal adjustments with the goal of meeting the requirements. The values provided are based on the respective peripheral industry standard, when applicable, and includes some assumptions about expected PCB trace delays. Once silicon is available, the product engineering team characterizes timing of the various peripherals. The data sheet values represent characterization data. 

In many cases there are trade-offs in a design that need to be considered and what must be done to benefit one function may compromising another. When this happens it may not be possible to meet all of our timing goals. So we publish the characterized values in the data sheet and leave some timing adjustments to the systems/PCB designer. 

This is why timing values may vary from one device to another. This is also the reason timing analysis should be performed on every peripheral using actual PCB delays. 

For the case mentioned in your E2E post, the effect of attached device min delay on the processor hold time should not be a problem since the processor to device clock delay and device to processor CMD/DAT delay will provide additional margin. However, the effect of processor min delay on the attached device hold time will be a problem if the system designer doesn’t insert at least 1.2ns additional delay on the CMD/DAT traces. 

Regards,

Sreenivasa

Hi Board designers, 

Information related to eMMC size

How much maximum memory size does AM6442 supports for eMMC memory?

There is no size limitation.  MMC0  (emmc controller) interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51)

I checked with the hardware and the software experts, and the answer is there are no limits or limitations.

Please use this guidance for selection of the flash for your project:

OSPI, GPMC interfaces are same across AM62, AM62A and AM62P. eMMC interface on AM62P supports upto HS400 projects and AM62/AM62A supports only HS200 speeds.

Regards,

Sreenivasa

Hi Board designers, 

The JEDEC eMMC standard defines internal pulls to be implemented in the eMMC device for data lines DAT1-DAT7. Immediately after entering the 4-bit mode, the device disconnects the internal pull-ups for DAT1-DAT3. Correspondingly, immediately after entering to the 8-bit mode the device disconnects the internal pull-ups for DAT1–DAT7.

The standard also defines host pull requirements for each signal except CLK, and says the host is expected to provide pull-ups to protect the CMD and DAT signals from floating when all device drivers are in a high-impedance state. Two pull-up types are defined for CMD, where R_OD is switched on and off by the host synchronously to open-drain and push-pull mode transitions. The other option is a fixed R_CMD pull-up when the host does not allow the switchable R_OD implementation.

Note: Most of the AM62x IOs are turned off by default to prevent any potential conflict with attached devices. This is done because these IOs support multiple signal functions via pin multiplexing and TI doesn't know what will be connected to multiplexed pins. External pulls may be required to hold inputs of any attached device in a valid logic state until software initializes the respective IOs. The CLK case described above is a good example, where an external pull should be used to protect the attached device from a floating input

How we determined the 47K value. Do we have recommendations on what these values should be?

All eMMC devices are required to turn on their internal pull-ups on DAT[7:0] to protect inputs from floating because it is not known if the eMMC device will be connected to a 1-bit host, 4-bit host, or 8-bit host.

There is not such protection for the CLK, CMD, and DAT[0] inputs because the eMMC device assumes it will be connected to a host that is always sourcing these signals.

That is not the case for some of our MMC ports. The IO cells associated our MMC ports implemented with SDIO buffer types will be turned off by default, which allows the eMMC CLK, CMD, and DAT[0] inputs to float.

CMOS inputs should never be allowed to float, so we tell customers they must install an external pull-down on the CLK signal and a pull-up on each of the CMD and DAT[0] signals for these MMC ports to protect the eMMC inputs until the device has booted and software has enabled the associated IOs and MMCSD host controller.

For these MMC ports, we never need to turn on our internal pulls for the CLK, CMD, and DAT[0] signals since the customer should be installing external pulls on these signals.

The eMMC device will turn off its internal pulls on DAT[3:1] when entering 4-bit mode or turn off its internal pulls on DAT[7:1] when entering 4-bit mode because it expects the host to provide this function on all of its DAT signals. This means we should be turning on our internal pull-ups on the same signals when entering 4-bit or 8-bit mode, at the same time the eMMC device is told to enter either of these modes. However, our eMMC software driver is not able to access the PADCONFIG registers. So we have decided to turn our DAT[7:1] internal pull-ups in one of the early boot codes so they are already turned on before the eMMC host enters 4-bit or 8-bit mode.

No external pulls are required for our MMC ports implemented with the eMMCPHY buffer type (MMC0 on AM64x, AM243x, and AM62Px) because the signals will be driven and/or pulled to valid logic states as soon as the processor is powered.
The eMMC standard requires the pulls to be in the range of 10k to 100k, with a recommendation to be in 10k to 50k range when operating at 1.8V. We typically recommend an external 47k pull-up on the CMD and DAT signals. This allows the combined parallel pull (internal in case the pullups are enabled unexpectedly + external pullup) resistance to remain within this range defined by the eMMC standard.

The eMMC standard doesn’t define a pull-down resistance for CLK, so we recommend an external 10k to reduce noise immunity when the signal is not driven.

Information related to clock pulldown 

e2e.ti.com/.../faq-am625-what-s-the-purpose-for-the-pull-down-r-on-mmc_clk

May I know what the purpose for the pull down R on MMC_CLK signal on TI EVM? May I know what the purpose for the pull down R on MMC_CLK signal on TI EVM? 
Most of the IOs associated with the AM62x device default to the off state, which means any attached device input without an internal pull resistor would be floating until software configures the pin to drive the signal. We use an external pull-down rather than an external pull-up since the clock signal is held in a low logic state when paused.

 Because there are cases where the clock is stopped or paused in a low logic state and the pull-down option is consistent with this logic state.

On the AM62A EVM, only CMD and Dat0 have pull-up.  What are the reasons that pull-up resisters on DAT[7:1] pins are not installed?

Because the eMMC standard requires all eMMC devices to turn on internal resistors for each of the DAT[7:1] pins until the device is configured to operate in 4-bit mode or 8-bit mode.  When the bus width changes any unused signals remain pulled high by internal pulls, but the others are turned off and the host is expected to turn on its internal pulls to hold the bus in a valid logic state while not driven.

You didn't ask about CLK, but there should be an external pull-down resistor installed on this signal to hold it low until the host is configured to drive the signal. This is required to prevent the eMMC clock input from floating until software initializes the respective pin multiplexing and clock source.

he internal pulls on most AM62Ax pins will be turned off until software initializes the respective PADCONFIG register. The state of each pin is defined in the datasheet.

The customer must ensure their system design doesn't allow input pins of attached devices to float until software turns on our internal pulls or drives a valid logic state on the signals.

In the eMMC use case, the eMMC device will perform this task by applying its internal pull-ups on the DAT[7:1] signals. External pull-up resistors will be needed for the DAT0 and CMD signals. An external pull-down will be required for the CLK signal.

(36) [FAQ] AM62A7: MMC0 Pull Resistor Requirements - Processors forum - Processors - TI E2E support forums

This e2e exchange: AM6442: eMMC pull-ups necessary or not?, results in a statement that the AM6442 requires no external pull resistors on the MMC0 interface, and that the processor will provide all required pull levels.  Is this also the case for the AM62A processors?

No. You must connect an external pull-down on CLK, and external pull-ups on CMD and DAT0 to prevent these eMMC device inputs from floating until software initializes the host controller and AM62Ax IOs associated with MMC0. The eMMC standard requires an eMMC device to have internal pulls turned on by default on DAT[7:1], so these signals do not require an external pull-up resistor. Software should turn on the respective internal AM62Ax DAT pull-ups when the bus width is increased from 1-bit mode to 4-bit or 8-bit mode.

This is required on AM62A because the IOs associated with MMC0 are implemented with standard dual-voltage LVCMOS IO cells with the capability of multiplexing additional signal functions to the respective device pins. Therefore, these MMC0 IOs are turned off by default since it is unknow what may be connected to these pins. That is not the case for AM64x since it's the MMC0 port is dedicated to eMMC.

(+) AM623: Problem Detecting eMMC at HS200 speed during 1.8V voltage switch. - Processors forum - Processors - TI E2E support forums

The effect you are describing by adding a series termination resistor seems to indicate a signal integrity issue. You mentioned testing modules. Does this mean the eMMC device is on a different PCB that the processor with eMMC host? If so, does your system maintain a constant signal trace impedance as the MMC0 signal transition across any board-to-board connector? Does any of your MMC0 signals cross split power/ground planes or transition from one reference plane to another such that a constant trace impedance is not maintained? 

Add a capacitor to any of the MMC0 signals can impact timing by slowing the signal transition relative to the other signals. This type of imbalance in signal load was not accounted for doing timing closure of the device. Getting improved results by adding a capacitor may indicate you have a timing issue in your system. It is acceptable to add capacitors as a debug step, but adding capacitors on the MMC0 signals should not be done in a production system. Did you ensure the signal trace delays in your system are within the limits defined in the datasheet MMC0 Timing Conditions table?

Regards,

Sreenivasa

Hi Board designers, 

Information related to clock measurement

What you observe on this signal depends on where you connected the probe, the bandwidth of your probe/scope, and quality of your scope probe ground. 

You will need a very high bandwidth probe and scope to observe short over-shoot, under-shoot, and non-monotonic events on the signal. I recommend using a low capacitance FET probe with a very-very short low loop inductance ground.

You will see a mid-supply step on the signal when probing near the source. This occurs because the output impedance of the MMC0_CLK output buffer, series termination resistor, and characteristic impedance of the PCB signal trace creates a voltage divider. The voltage divider output is applied to the source end of the PCB signal trace. This voltage propagates down the trace to the far end where it encounters a high impedance load which causes a in-phase reflection that returns to the source. Therefore, the voltage transition observed on the far end will be a continuous transition between VSS and VDD. The is not the case for the source end, as it steps to a mid-supply determined by the voltage divider values and the transition only continues to VDD or VSS once the reflection returns from the far end. You need to select a series resistor value that allows the MMC0_CLK pin to step through the voltage of (VDDSHV4 / 2) without pause. I suggest the step observed on the MMC0_CLK pin should be at least 200mv above (VDDSHV4 / 2) on the rising edge and at least 200mv below (VDDSHV4 / 2) on the falling edge.

Regards,

Sreenivasa

Hi Board designers, 

Information related to eMMC reset configuration 

[FAQ] AM62x: How to check and configure eMMC flash RST_N signal to support WARM_RESET from eMMC booting on AM62x-SK E2

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1168342/faq-am62x-how-to-check-and-configure-emmc-flash-rst_n-signal-to-support-warm_reset-from-emmc-booting-on-am62x-sk-e2

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1500901/tda4vm-this-is-a-question-about-emmc-boot/5769543

In case of eMMC ,reset can be done in 3 ways:

• CMD0
• HW_Reset
• Power cycle 

CMD0:(S/W RESET)

Sending CMD 0 with specfic arguments will do software reset of the eMMC .

H/W reset:

The h/w reset can be done by sending the RST_n signal .

By default, the RST_n signal is temporarily disabled in the dev

ice.
• The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.

I am also attaching the JEDEC SPEC FOR EMMC which contains the details regarding resetting the eMMC which I would recommend going through:

JESD84-B51 (1).pdf

Hi Board designers, 

Information related to eMMC implementation for AM64x and AM62x

(39) SK-AM62: eMMC: Cannot write to MMCSD0_SS_PHY_CTRL_1/2/3 registers - Processors forum - Processors - TI E2E support forums

The MMC0 port on AM64x has a analog PHY with a DLL that is used to insert appropriate delays and controls most pin functions.  This port only supported eMMC signal functions operating at 1.8V.

The MMC1 port on AM64x uses a different method to insert delays and the IOs associated with this port are implemented with dual-voltage LVCMOS IO cells that were optimized for MMC/SD signal functions. This port supports multiple signal functions via pin multiplexing and they can operating at 1.8V or 3.3V.

The MMC0 port on AM62x is basically an 8-bit implementation of the AM64x and AM62x MMC1 port.

MMC0 on AM62x supports several eMMC and SD Card standards. Please refer to the MMCSD timing sub-section of the AM62x datasheet Timing and Switching Characteristics section for data transfer modes supported.

The MMC0 port does not provide the card detect and write protect inputs that would typically be connect to an SD Card connector. This port only supports SD Card data transfer modes to allow connectivity of embedded SDIO devices like WiFi. This port supports 1.8V or 3.3V, but 1.8V should be used in most cases since 1.8V provides more timing margin, which may be required for the faster data transfer modes.

The eMMC standard requires a device to provide internal pull-ups on DAT[7:1] by default.  These internal pull-up resistors will hold the DAT[7:1] signals in a valid logic state until the device is put into 4-bit or 8-bit mode, where the internal pull-ups are turned off on DAT[3:1] when placed in 4-bit mode or DAT[7:1] when placed in 8-bit mode. The AM62x internal pull-up resistors need to be turned on for the respective signals before the eMMC device is placed in 4-bit or 8-bit mode so signal are not allowed to float. A value of 0x60000 will turn on the AM62x internal pull-up and enable the input buffer for respective pins. 

We recommend an external pull-down resistor on CLK, and an external pull-up resistor on the DAT0 and CMD signals. This is required to hold these signals in a valid logic state since our IOs associated with these signals are off by default after power is applied, and the eMMC device does not have internal pulls on these pins. If you follow this recommendation, the internal pulls should remain off for each of these pins. A value of 0x40000 will turn on the internal pull-down and enable the input buffer on CLK. It is not clear why the internal pull-down and  input buffer is being turned on for CLK since we expect an external pull-down on this signal and the pin operates as an output only. As mentioned above a value of 0x60000 will turn on the AM62x internal pull-up and enable the input buffer for respective pins. So it is not clear why the internal pull-up is being turned on for DAT1 and CMD since we expect an external pull-up on these signals. 

I would not expect there to be an issue with turning on the input buffer for CLK, but it is not necessary.

I also do not expect an issue turning on internal pulls for signals with external pulls, as long as the external pulls are not in contention with the internal pulls and the total resistance doesn't go below the minimum pull resistance defined by the eMMC standard.

Regards,

Sreenivasa

Hi Board designers,

Inputs regarding HS200

(+) AM625: emmc HS200 Occasional IO errors - Processors forum - Processors - TI E2E support forums

The HS200 data transfer mode requires the read data path to be tuned for optimum timing. This means HS200 read timing varies based on the final tuning results. Therefore, it is not possible to define the device input requirements for HS200.

The eMMC standard requires an eMMC device to have internal pull-up resistors on DAT[7:1] turned on by default. The eMMC device will turn off the DAT[3:1] resistors once the device is switched to 4-bit mode, or will turn off the DAT[7:1] resistors once the device is switched to 8-bit mode. At this point the eMMC host must turn on its respective internal pull resistors, or external pulls must be used.

We require external pulls on the CLK, CMD, and DAT0 signals to hold the eMMC inputs in a valid logic state because the AM62x IOs are turned off by default. The eMMC device internal resistors will hold the DAT[7:1] inputs in a valid logic state until software has initialized the peripheral.

The eMMC boot code never enables the internal resistors on CLK, CMD, or DAT0 because they should already have external pulls as described above. However, it must turn on the AM62x DAT[7:1] internal resistors because the eMMC device will turn its internal resistors off once it enters 8-bit mode.

The pull resistance value of the AM62x internal pulls is defined in the SDIO Electrical Characteristics table found in the datasheet. The pull resistance value of the eMMC device internal pulls is defined in the eMMC standard. The pull resistance of the external pull resistors should be selected to be compliant to the eMMC standard.

FYI: There is an error in the eMMC Pin Usage table you inserted above. There is no pin named MMC0_CLKLB.

We recommend an external pull-down on CLK, an external pull-up on CMD, and an external pull-up on DAT0. The resistors values should be in the range of 15k to 50k ohms.

You only enable the AM62x internal pulls which are turned off in the eMMC device. The eMMC device will only turn off the DAT[3:1] resistors when the device is switched to 4-bit mode, so you would only need to turn on the AM62x internal pulls for DAT[3:1] when operating in 4-bit mode.  You would turn on the AM62x internal pulls for DAT[7:1] when operating in 8-bit mode.

The AM62x internal pulls are controlled via the respective PADCONFIG register.

Regards,

Sreenivasa

Hi Board Designers,

Inputs related to the Pin attributes for MMC0 signals for AM64x and AM62Px 

AM62P5-Q1: HW:  Confirmation of MMC0 Pin specifications

Please tell me the specifications of "Electrical Characteristics" of eMMCPHY.

AM62P
Data sheet
www.ti.com/.../sprsp89
AM62Px Sitara Processors datasheet (Rev. B)

The MUX MODE, DSIS, and MUX MODE AFTER RESET columns will remain blank for these pins since these cells in the table are not applicable because the pins are implemented with a hard macro PHY, which doesn't support the pin multiplexing logic.

The HYS column should have a value of "No" since the input buffers associated with the PHY does not have hysteresis.

The BALL STATE DURING RESET and BALL STATE AFTER RESET values will be as shown below:

MMC0_CLK - On / Low / Off - On / SS / Off
MMC0_CMD - On / Off / Up - On / SS / Up
MMC0_DS - On / Off / Down - On / Off / Down
MMC0_DAT[7:0] - On / Off / Up - On / SS / Up

For electrical characteristics refer to the eMMCPHY Electrical Characteristics defined in the datasheet.

Regards,
Sreenivasa

Hi Board Designers,

Inputs based on eMMC boot board bring-up 

How to enable warm reset from u-boor or kernel when booting from eMMC on AM62x-SK board
1. Micron eMMC datasheet
RST_n: The RST_n signal is used by the host for resetting the device, moving the device to the pre-idle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.

2. The eMMC hardware reset signal RST_n can be permanently enabled by programming eMMC ECSD bits in either u-boot or kernel:
a) @U-boot: => mmc rst-function 0 1
b) @Kernel: mmc hwreset enable /dev/mmcblk0

3. AM62x-SK E2 test:
a) Pre-programming eMMC ECSD bits @kernel
root@am62xx-evm:~# mmc extcsd read /dev/mmcblk0 | grep -i RST
H/W reset function [RST_N_FUNCTION]: 0x00 => RST_n is NOT enabled on AM62x-SK E2
b) Programming eMMC ECSD bits @u-boot
=> mmc rst-function 0 1
c) Post-programming eMMC ECSD bits @kernel
root@am62xx-evm:~# mmc extcsd read /dev/mmcblk0 | grep -i RST
H/W reset function [RST_N_FUNCTION]: 0x01

POR issue on customer board

Observations:

1. The SoC MCU_PORZ input pin goes to low after PMC watchdog reset or cold reset button click.
2. The PORZ_OUT pin outputs low after PMC watchdog reset or cold reset button click.
3. The SoC doesn't boot as expected from EMMC Boot0. The SBL doesn't start.
4. Connecting the debugger to WKUP core after the reset while in EMMC boot mode, The PC is at address 0x41801954.
5. We have found that connecting the debugger while the boot mode configuration is set to UART mode, the PC is also at address 0x41801954. 
6. There are no output on any of the UART pins (WKUP, MCU, MAIN).

Questions:

1. Based on the observations, Is the SoC booting on UART mode after the reset ? 
2. Is the address '0x41801954' part of the ROM code execution ?
3. How to confirm that the SoC reset successfully ?

Here is the Boot mode pin configurations:

eMMC --> 0000000001001011
UART -->  0000000000111011

We have detected the issue. The ROM code failed to boot from eMMC and went to the backup mode. And that was caused by the eMMC not resetting due to RST_N_FUNCTION in eMMC ECSD is not set. Enabling the RST_N solved the issue for the PMIC watchdog reset and cold reset by HW. 

AM6442: How does EMMC warm reset take effect - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

AM62P-Q1: Board fails to reset properly when booting U-Boot from eMMC - Processors forum - Processors - TI E2E support forums

The issue was resolved after running the CMD

mmc rst-function 0 1

(+) AM623: when in eMMC boot Mode, facing rebooting failed issue both in u-boot (reset) and linux (reboot) - Processors forum - Processors - TI E2E support forums

[FAQ] AM62x: How to check and configure eMMC flash RST_N signal to support WARM_RESET from eMMC booting on AM62x-SK E2 - Processors forum - Processors - TI E2E support forums

AM62A7-Q1: eMMC reset input - Processors forum - Processors - TI E2E support forums

The GPIO option was included on the EVM in case we found a reason software need to reset the eMMC device without resetting the entire system. I ask our eMMC software expert and was told the eMMC driver currently doesn't provide any provision to reset the eMMC device via a GPIO. Therefore, the GPIO reset capability appears to be an option that may be implemented in the future if there is a need to reset the eMMC device without resetting the entire system.

Regards,

Sreenivasa

Hi Board Designers,

Inputs related to MMC0 interface issues

(+) AM6442: AM6442BSEFHAALV - eMMC interface - Processors forum - Processors - TI E2E support forums

AM6442: AM6442BSEFHAALV - eMMC interface

The external pulls should not impact data transfer. The external pulls are only needed to hold the signals in a valid logic level when not driven. For example, the eMMC specification requires an eMMC device to have internal pulls on its DAT[7:1] pins turned on by default. The eMMC device does not have internal pulls on its CLK, CMD, and DAT0 pins. You need to have external pulls on these signals to prevent these signals from floating until software has initialized the AM64x device. The current recommendation is to include an external pull-down on CLK, and an external pull-up on CMD and DAT0.

Was your PCB design to be compliant to the PCB delays defined in the MMC0 Timing Conditions table?

Have you check the signal quality of the eMMC signals on you PCB implementation?

How many PCB assembly have you tested?

Have you been able to determine if your issue is the result of write or read operations?

Regards,

Sreenivasa

Hi Board Designers,

Inputs related to supported interfaces on MMC0 and MMC1

You should be looking at the MMC0 - eMMC Interface section in the Timing and Switching Characteristics section of the datasheet.  This is where the datasheet defines valid modes of operation.

(+) AM6442: Why only emmc0 can support emmc flash - Processors forum - Processors - TI E2E support forums

Because the design team only closed timing of the MMC0 peripheral for operating with eMMC devices and only closed timing of the MMC1 peripheral for operating with SD Cards.

AM64x does not support SD Card on MMC0. More details provided below.

It was not possible to close timing on the MMC0/MMC1 ports for them to be compliant with both eMMC and SD Card standards, so MMC0 timing was optimized for eMMC and MMC1 timing was optimized for SD Card.  You may find MMC0 timing is compliant to timing requirements of some SDIO devices, but you would need to perform a detailed timing analysis using system specific PCB delays, switching characteristics, and timing requirements of each device to confirm

The external pull requirements vary based on the PHY implemented for a specific host port and the attached device. The PHY implemented for the AM64x MMC0 port only supports eMMC devices and does not require external pulls to hold the attached device in a known state until the port is initialized because the MMC0_CLK pin is driven internal pulls are automatically turned on as soon as the AM64x device is powered. That is not the case for MMC1.  

(+) AM6442: Does MMC1 controller support Wifi SDIO devices ? - Processors forum - Processors - TI E2E support forums

There are slight timing differences between the eMMC standard and the SDIO/SD Card standard. We were not able to close timing on MMC0 such that it would meet both standards, so we descoped SD Card support from MMC0.

The hardware development team was ask to include the Wifi SDIO device in their design to showcase the Wifi SDIO device and provide a software development platform. They found it was possible to get this specific Wifi SDIO device to work on MMC0 with a specific PCB implementation after performing a timing analysis that included actual timing parameters from each device and actual PCB trace delays. They may have adjusted trace lengths to optimize timing margin.

MMC0 may work with some SDIO devices, but it is your responsibility to design a system that does not violate timing requirements of either device. 

Note: MMC0 only supports 1.8V IO.

Regards,

Sreenivasa

Hi Board Designers,

E2E for reference:

(+) [FAQ] AM623: Can eMMC0 support DDR50 mode - Processors forum - Processors - TI E2E support forums

From the Hardware perspective, the AM62x devices support three eMMC data transfer modes on MMC0. The modes supported are defined in the MMC0 timing section of the datasheet. The device supports eMMC Legacy SDR, eMMC High Speed SDR, and eMMC HS200 modes. The device does not support the eMMC High Speed DDR mode.

Note: The SD Card UHS-I DDR50 is supported which may seem strange since eMMC High Speed DDR is very similar, but there are small timing differences that prevented the design team from being able to close timing for eMMC High Speed DDR mode.

The software team found some configuration issues that could be problematic and fixed them in the SDK version Bin referenced above. I suggest you encourage the customer to use the latest MMC software driver for a more robust system.

(+) AM623: copy files to eMMC trigger CQE error - Processors forum - Processors - TI E2E support forums

(+) AM623: How to reduce eMMC speed - Processors forum - Processors - TI E2E support forums

(+) AM623: Why can serial resistor eliminate eMMC IO error - Processors forum - Processors - TI E2E support forums

#1. What is the purpose of 0ohm resistor for MMC0_CLK? 

#2. Software turn on DAT pulls when changes the mode, is pulls must required on DAT pins? if so, why eMMC device turn it off from on during switch?

#3. Is it implemented in SDK to turn on DAT pulls when changes mode? did not find padconfig information in driver sdhci_am654.c

1) The series resistor provides an option to install a 10 ohm to 33 ohm impedance to help attenuate reflections that return from the far end of the signal trace if needed to resolve signal integrity issues.

2) The pull-up resistor R399 is Do Not Install (DNI), so it is not pulled up.

Tuning is used in HS200 mode to optimize receive timing. This is needed because the attached eMMC devices doesn't provide a data strobe (DS) signal during HS200 mode. We need to compensate for the PCB and attached eMMC delays that vary across systems so the capture clock transition can be centered in the data valid window. The delay being adjusted during tuning is in the receiver DAT/CMD capture clock inside the AM62x device

The respective datasheet Timing Conditions table defines the maximum PCB delay mismatch allowed for each data transfer mode. Our design team accounts for this PCB trace delay mismatch during timing closure of the peripheral.

Attaching some documentation on ISI which can help address this question.ISI_SSO_basics.pptx

e2e.ti.com/.../5896426

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1438851/am625-sd-card-flash-emmc

(+) AM625: MMC0(eMMC) Pull Up - Processors forum - Processors - TI E2E support forums

The 49.9K resistor has specific tolerance requirements and hence we have been recommending 47K to use a standard tolerance resistor.

See below. This is the AM62L EVM

We are in the process of updating the Sk-AM62B-P1.

You could use 10K but there is a caution note that the pullup value may not meet the eMMC specifications in case the internal pulls are enabled unexpectedly.

With 47K, the parallel pullup value is still within the eMMC recommendation.

Note on a custom board debug:

And also according to the FAQ on deign recommendations/commonly observed errors during custom board HW design on eMMC memory interface:
• We recommend external pull-ups on the CMD and DAT0 signals and an external pull-down on the CLK signal. The eMMC standard also says 10k pull-ups are the min value, so we do not recommend using a 10k resistor because it may be less than 10k. We typically recommend using 47k resistors to minimize loading on the signals since the pulls are only used to hold the signals in a valid logic state when not driven.
The customer’s question:
So like to understand if TI have any issue (any negative consequences) if we change MMC0_CMD line pull-up from 47K to 10K (R15(CMD)=10K? Will it affect relative timings to other eMMC signals?

The signal quality and the clock to data timing measurements taken look like what I would expect to see. Therefore, I suspect this issue is related to the read data path since it is not possible to measure the timing relationship of the signals entering our capture flops after the internal tuning delays.

Does the customer have a way to write known data into the eMMC device and verify the data was written correctly when configured to operate at a reduced operating frequency. Then read the known data pattern at the higher operating frequency and compare it to what was expected as a way to better understand if the error is being introduced during reads or writes.

I still think we need to make sure they are using the latest software.

The CMD pull resistor value change should not be required. I suspect the previous software configuration was operating on the very edge of valid timing and the pull resistance change from 47k to 10k caused a slight shift in signal timing, which was just enough to allow valid data transfers. This pull-up resistance difference should not have any impact on data transfers when everything is configured correctly.

The primary purpose of the pull-up resistor on CMD is to hold the signal in a valid logic state when not being driven by either device. The eMMC standard allows the CMD pull-up to be in the range of 4.7k to 50k when operating at 1.8V, so change the value to 10k should not cause any problems. However, the reduced resistance will consume more power when the signal is driven low.

I agree with not changing any of the DAT pull-up values since the eMMC standard requires them to be in the range of 10k to 50k when operating at 1.8V. Even a 10k resistor with a 1% tolerance could violate the min resistance range. This is why we recommend 47k pull-up resistors, which allows customers to select a resistor with 5% tolerance without violating the eMMC standard.

The latest SDK has fixed several bugs in the MMC driver, which related to the MMC CLK timing. Those changes resolved different failure cases for HS200 mode. The 50MHz issue was one of those cases.

Regards,

Sreenivasa

HI Board Designers, 

(+) AM62L: MMC - Processors forum - Processors - TI E2E support forums

Inputs related to supported standards

Do all three MMC/SD buses support eMMC 5.1, SD 3.0, and SDIO Version 3.0?

2、What does the content shown in the following picture mentioned in the TRM manual mean? Does it support SD 4.10 and SDIO 4.0? So, should we follow the data manual or the TRM?

The next revision of the AM62Lx datasheet will be updated to show with the following list of devices and data transfer modes supported for each MMC instance.

The MMC0 port supports connections to an eMMC device or embedded SDIO device. It does not support removable SD Cards.

The MMC1 and MMC2 ports support connection to a removable SD Cards or embedded SDIO device. They do not support eMMC devices.

What does the content shown in the following picture mentioned in the TRM manual mean? Does it support SD 4.10 and SDIO 4.0? So, should we follow the data manual or the TRM?

For the SDIO specifications, please follow the data sheet.

The references to 4.x in the TRM will be updated.

egarding the MMC interface of AM62Lx, does MMC0 support a 1-bit wide data bus or a 4-bit wide data bus? And do MMC1 and MMC2 support a 1-bit wide data bus?

Is this a generic query or do you have an use case for the query.

As a general answer, MMC0 should be able to support 4-bit or 1-bit and MMC1/MMC2 should be able to support 1-bit.

I ever have similar support needs to support 2 eMMC, even one can be 4bit mode. which was supported on AM335x, but new AM62x can only support one, is it just not verified/tested? or the IP can't support 4-bit eMMC on MMC1?

eMMC is only supported on MMC0. We did not close timing of any other MMC port to be compliant to the eMMC timing requirements.

Regards,

Sreenivasa

Hi Board Designers, 

Inputs related to eMMC supply connection and transient current

(4) AM6421: Does the connectino of VDDS_MMC0 and 1.8v for analog cause some noises to the analog IP ? - Processors forum - Processors - TI E2E support forums

The VDDS_MMC0 power rail sources digital output buffers which will result in large transient currents as the outputs transition multiple digital signals from low to high at the same time. The large current transients can introduce noise on its power source, but the noise can be minimized with appropriate decoupling capacitors and low inductance PCB connections. Therefore, power supply noise is function of the specific system implementation.

Combining digital loads and analog loads on a shared power source may be possible with the appropriate system implementation, but creating separate power sources for the digital loads and analog loads will reduce the risk associated with the digital loads creating noise on the analog power rails.

The system designer needs to use appropriate decoupling capacitors and PCB layout to minimize noise on a shared power source. 

(4) AM6421: Isolation of VDDS_MMC0 and 1.8V analogue systems by π type of filter - Processors forum - Processors - TI E2E support forums

VDDS_MMC0 is powering the IO buffers that drive the clock, command, and data signals associated with the MMC0 port. The worst-case transient current for the VDDS_MMC0 power rail occurs when all of these 10 signals toggle at the same time. To calculate an example transient current, assume the MMC0 output buffers are configured to a 50ohm source impedance, and the PCB signal traces were designed to have 50ohm AC characteristic impedance. When the output buffer toggles, the IO operating voltage (1.8V) would be applied to the series combination of the output buffer source impedance and the PCB trace impedance. In this example, the transient current for a single output buffer would be 1.8V/100ohms = 18mA. You need to multiply this value by 10 to account for the worst-case condition of all signals changing at the same time. This means the worst-case transient current for the VDDS_MMC0 pin in this example would be 180mA.

The filter would need to be designed to ensure the voltage applied to VDDS_MMC0 pin would never drop below the minimum Recommended Operating Condition value when this worst-case transient current is consumed by the AM64x device. It is also important to confirm the filter doesn't have a resonance at the transient frequency.

It may be necessary to confirm the filter performance by simulating power quality using models of the filter components and actual LRC characteristics extracted from the PCB design. The only other choice is to design a system using best design practices and modify the design as necessary until you are able to achieve good power quality.

Regards,

Sreenivasa

Hi Board Designers, 

Inputs related to eMMC boot and extcsd

e2e.ti.com/.../5539147
e2e.ti.com/.../faq-sk-am62-how-to-flash-emmc-using-usb-dfu-on-am62x-sk-e2
e2e.ti.com/.../am62a7-q1-faq-how-to-enable-emmc-uda-boot-mode-and-emmc-boot-mode-on-am62a
e2e.ti.com/.../sk-am62-lp-am62x-emmc-boot-fails-after-successful-dfu-flash
e2e.ti.com/.../faq-am62x-how-to-check-and-configure-emmc-flash-rst_n-signal-to-support-warm_reset-from-emmc-booting-on-am62x-sk-e2
e2e.ti.com/.../am625-set-emmc-extcsd-register-in-otp-keywriter
e2e.ti.com/.../5728321
e2e.ti.com/.../6022835

EMMC standard
e2e.ti.com/.../5769543
Clarification on ROM BOOT processing
e2e.ti.com/.../5768566
e2e.ti.com/.../5919688
After enter mmc rst-function 0 1 in uboot, my EVM can normally reboot.
We compared the signal of RESETSTATz during reboot and finally determined that there was an issue with the connection of our board's RSTn pin. After properly connecting it and entering the command "mmc rst-function 0 1", the reboot command now functions correctly.
e2e.ti.com/.../am625-booting-from-emmc
e2e.ti.com/.../am625-emmc-boot-not-working
e2e.ti.com/.../4551419
e2e.ti.com/.../4733810
e2e.ti.com/.../4506162
A1. MMC/eMMC port is determined by BOOTMODE pins, and from which eMMC partition (boot1/boot2/UDA) R5-SPL boots from is solely by the eMMC EXTCSD[179]
A2. tispl.bin (ATF + OPTEE + A53-SPL) booting media is determined in R5-SPL as listed below, and essentially by BOOTMODE pins, but changle by user as needed.
git.ti.com/gitweb
ECU stuck in Resetting from linux using reboot command in EMMC boot mode, despite it's working using same binary in booting from SdCard? .

Did you test eMMC on TI AM62x-SK board?
How to enable warm reset from u-boor or kernel when booting from eMMC on AM62x-SK board
1. Micron eMMC datasheet
RST_n: The RST_n signal is used by the host for resetting the device, moving the device to the pre-idle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.

2. The eMMC hardware reset signal RST_n can be permanently enabled by programming eMMC ECSD bits in either u-boot or kernel:
a) @U-boot: => mmc rst-function 0 1
b) @Kernel: mmc hwreset enable /dev/mmcblk0

3. AM62x-SK E2 test:
a) Pre-programming eMMC ECSD bits @kernel
root@am62xx-evm:~# mmc extcsd read /dev/mmcblk0 | grep -i RST
H/W reset function [RST_N_FUNCTION]: 0x00 => RST_n is NOT enabled on AM62x-SK E2
b) Programming eMMC ECSD bits @u-boot
=> mmc rst-function 0 1
c) Post-programming eMMC ECSD bits @kernel
root@am62xx-evm:~# mmc extcsd read /dev/mmcblk0 | grep -i RST
H/W reset function [RST_N_FUNCTION]: 0x01

(5) [FAQ] AM62x: How to check and configure eMMC flash RST_N signal to support WARM_RESET from eMMC booting on AM62x-SK E2 - Processors forum - Processors - TI E2E support forums

Explanations on the issue observed:
Micron eMMC datasheet [https://www.mouser.com/datasheet/2/671/micron_technology_mict-s-a0006806196-1-1759129.pdf]
• RST_n: The RST_n signal is used by the host for resetting the device, moving the device to the pre-idle state.
• By default, the RST_n signal is temporarily disabled in the device.
• The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.

How to check eMMC RST_n by reading eMMC ECSD register
Boot to Linux, and kernel log below shows RST_n is NOT enabled on eMMC ECSD on one AM62x-SK E2 board
root@am62xx-evm:~# mmc extcsd read /dev/mmcblk0 | grep -i RST
H/W reset function [RST_N_FUNCTION]: 0x00

How to enable eMMC RST_n by programming eMMC ECSD register
The eMMC hardware reset signal RST_n can be permanently enabled by programming eMMC ECSD bits one-time only either @u-boot OR @kernel as listed below
• @U-boot: => mmc rst-function 0 1
• @Kernel: mmc hwreset enable /dev/mmcblk0. Note that “/dev/mmcblk0” is an example of the eMMC device mounted in Linux kernel.

The kernel log below shows eMMC RST_n is enabled, and any WARM_RESET option would work now.
root@am62xx-evm:~# mmc extcsd read /dev/mmcblk0 | grep -i RST
H/W reset function [RST_N_FUNCTION]: 0x01

e2e.ti.com/.../5227189

The ROM boots the SBL/SPL from the different interfaces in the following sequence:

Primary boot from Primary Bootmedia
Redundant boot, if supported, from Primary Bootmedia
Backup Bootmedia
In the case of eMMC primary boot, the ROM only supports redundant boot from offset 0x400000 for UDA RAW bootmode. The ROM also does not support booting from the Boot1 partition if booting from the Boot0 partition fails.

Now, if booting Linux OS, the UDA RAW bootmode and therefore redundant boot capability can't be leveraged because the partition table would need to be at offset 0x0 of UDA.

In short, if booting Linux OS, leveraging redundant boot for eMMC is really not possible. However, the customer can still leverage the Backup Bootmedia.

Taking into account all of the above, following are the different options:

1) eMMC Alternate (Boot0 or Boot1 partition)

Primary boot => 0x0 offset of either Boot0 or Boot1 partition as configured in the EXTCSD register of eMMC.
Redundant boot => Not possible.
Backup boot => Can be anything according to the backup bootmodes supported as listed in the TRM.
2) eMMC UDA RAW

Primary boot => 0x0 offset but not possible if booting OS which requires partition table at 0x0 offset.
Redundant boot => Possible with careful design. Reserve one partition that covers the offset 0x400000. Use this partition as RAW partition for flashing SBL/SPL at 0x400000.
Backup boot => Can be anything according to the backup bootmodes supported as listed in the TRM.
3) eMMC UDA FS

Primary boot => tiboot3.bin image in the FAT partition
Redundant boot => Not possible
Backup boot => Can be anything according to the backup bootmodes supported as listed in the TRM.

e2e.ti.com/.../4556423
eMMC boot partition size is pre-configured by eMMC vendor. The boot partition size is defined by eMMC read only EXTCSD[226] register as listed below:
Boot Partition size = 128Kbytes × BOOT_SIZE_MULT
For most of embedded system with eMMC, the commonly eMMC usage:
- eMMC boot partitions (boot0/boot1): bootloader (i.e. u-boot)
- UDA: rootFS, which can be further partitioned depending on user case, i.e. read-only rootFS, writeable FS etc...
Booting from eMMC boot partition is the default eMMC boot option in TI Linux SDK:
software-dl.ti.com/.../UG-Memory.html

e2e.ti.com/.../am623-does-emmc-have-compatibility-problem-with-dfu-fw-upgrade

e2e.ti.com/.../5634844
e2e.ti.com/.../4015636
e2e.ti.com/.../tda4vm-q1-tda4vm-emmc-switch
e2e.ti.com/.../4116759
e2e.ti.com/.../3634976
e2e.ti.com/.../4761402

Regards,

Sreenivasa

Hi Board Designers, 

Inputs related to Incorrect Mapping of Data Lines

One problem was Linux reads ext_csd to understand flash quirks but if lines are swapped , we kept getting errors as invalid ext_csd

1-bit to 8.bit interface transition can include reading data pattern and CRC from the memory device and may need to be bypasses when data bits are swapped.

There is no checksum that is being received by the host after eMMC writes, so there is no concern on the reads or writes  that are initiated on-board.

The eMMC driver/software provided as part of the SDK is unlikely to work based on my internal discussion.

The software is expected to be aware of the swapping. 

There are a number of checks that are done when accessing eMMC memory including reading or wring to the EXTCSD.

The software may need to bypass some of the checks and also change the bits for some of the read/writes to function.

Given the number of changes that may be required, it is unlikely you will be able to some quick changes and use eMMC interface with bits swapped.

The primary boot functionality may also be a concern since the bootmode is interfaced in 8-bit mode.

if you are looking to check the hardware functionality or perform basic eMMC access test, you may be able to test with the bits swapped.

 if data is written beforehand, software may swap the two bits to read  the right data. If data is written by the system/SoC, then no intervention is needed - you write "wrong" data, then you read "wrong" the result will be "right" data.

https://www.issi.com/WW/pdf/IS21_22ES04G.pdf

http://www.zeroplus.com.tw/E-paper/201207_en/images/201207-eMMC_en.pdf

(+) AM6442: The AM6442 fails to boot with 16GByte capacity eMMC - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hi Board Designers, 

Inputs related to recommended pulldown value for the attached memory device pulldown:

Memory interface peripherals pulldown value AM62x or Am64x 

I have a few customer using 1K pulldown for some of the signals from the SOC mostly for memory interfaces.

Wanted to get your thoughts on the use case.

The current draw from the IO seems more and could affect the VOH. Any thoughts on the use case please.

I agree the 1k resistor could impact the VOH level to the attached device, and it could also impact our VIHSS level if our receiver is turned on. 

The customer should run a simulation of their system using the IBIS models of each device connected to the signal to determine if the output can achieve an appropriate levels after accounting for the output buffer drive capability, worst case pull resistance, and worst case leakage of all attached components.  I would suggest they consider a 4.7k if there is a concern with 10k.

information on sizing of external pulls.

A resistor mus be selected that is able to hold the signal above the steady-state high (VIHSS) or below the steady-state low (VILSS) based on the signals worst-case combination of leakage, which will be the sum of the max leakage of all attached devices. 

For example, if it is assumed AM62P is connected to a single UART device that has a max leakage of 5uA when operating at 1.8V.  The worst-case leakage would be 10uA + 5uA = 15uA.  VIHSS for the LVCMOS IO cell operating at 1.8V is 0.85 x VDD = 1.53V.  A pull-up resistor value would need to be at less than 18k ohms to hold the voltage above 1.53V for a worst-case leakage of 15uA.  It is suggested to use a value that is less than 18K ohm for this example.

Input related to ANDing logic:

after each reboot, RESETSTATz will be pulled low for 220 µs, and eMMC_RSTn is affected by the action of RESETSTATz.

 AM2434: What is effect of warm reset? 

Can you please confirm eMMC_RSTn (RST_N) pin function (Reset input) has been enabled in the eMMC device (eMMC
non-volatile configuration space) for the reset logic to be functional

(+) [FAQ] AM62x: How to check and configure eMMC flash RST_N signal to support WARM_RESET from eMMC booting on AM62x-SK E2 - Processors forum - Processors - TI E2E support forums

Explanations on the issue observed:
Micron eMMC datasheet [https://www.mouser.com/datasheet/2/671/micron_technology_mict-s-a0006806196-1-1759129.pdf]
• RST_n: The RST_n signal is used by the host for resetting the device, moving the device to the pre-idle state.
• By default, the RST_n signal is temporarily disabled in the device.
• The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.

How to check eMMC RST_n by reading eMMC ECSD register
Boot to Linux, and kernel log below shows RST_n is NOT enabled on eMMC ECSD on one AM62x-SK E2 board
root@am62xx-evm:~# mmc extcsd read /dev/mmcblk0 | grep -i RST
H/W reset function [RST_N_FUNCTION]: 0x00

How to enable eMMC RST_n by programming eMMC ECSD register
The eMMC hardware reset signal RST_n can be permanently enabled by programming eMMC ECSD bits one-time only either @u-boot OR @kernel as listed below
• @U-boot: => mmc rst-function 0 1
• @Kernel: mmc hwreset enable /dev/mmcblk0. Note that “/dev/mmcblk0” is an example of the eMMC device mounted in Linux kernel.

The kernel log below shows eMMC RST_n is enabled, and any WARM_RESET option would work now.
root@am62xx-evm:~# mmc extcsd read /dev/mmcblk0 | grep -i RST
H/W reset function [RST_N_FUNCTION]: 0x01

H/W reset function [RST_N_FUNCTION]: 0x01

Regards,

Sreenivasa

Hi Board Designers, 

FYI, inputs related to eMMC waveforms

 AM6442: MMC0- eMMC interface timing in HS200 

The OTAPDLYSEL value of 0x7 has a delay variation that can range from 0.99ns to 3.28ns, where this delay range represents what can be expected across process, voltage, and temperature variations of the device. We do not define delay range for any other value of OTAPDLYSEL since this configuration should provide appropriate setup and hold time to the attached device as long as you meet the PCB trace length requirements defined in the Timing Conditions table

 AM6442: AM6442BSEFHAALV - eMMC interface 

The external pulls should not impact data transfer. The external pulls are only needed to hold the signals in a valid logic level when not driven. 

 AM62A7: Emmc power down interface 

.(+) AM6442: AM6442: eMMC CQE recovery problem - Processors forum - Processors - TI E2E support forums

 RE: AM6421: AM64x Booting through eMMC not working 

 RE: AM62L: Distorted eMMC HS200 Clock Waveform 

Currently no performance issue observe with eMMC. we also take measurement with Series resistor (R1) changed to Zero Ohm. See Below

 AM3358: A ringing problem of eMMC interface 

The resistor doesn't eliminate the non-monotonic transition. It shifts the voltage away from the input buffer switching threshold voltage, where it is less likely to create a glitch on the looped back clock going back into the processor. The only way to resolve the clock glitch issue is install a 33 ohm series termination resistor located very close to the AM335x pin. The trace length between the processor pin and the series resistor should be as short as possible.

What's the largest eMMC card that the AM67 can address?

In the AM67 datasheet, you can find that is is compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0.

As long as the eMMC/SD card is compliant with these standards, the AM67 should support it.

(+) AM67: eMMC interface capacitance - Processors forum - Processors - TI E2E support forums

 https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1597000/am67-emmc-usage 

 RE: TDA4VE-Q1: TDA4VE-Q1: DDR Memory & eMMC Selection 

Regards,

Sreenivasa

Hi Board Designers,

Inputs related to AM6421: RESETSTATz output during ROM boot

During a successful QSPI boot, I have captured the following signals: MCU_PORz, RESETSTATz, OSPI_CLK, OSPI_CS.  I'm observing that roughly 35mS after RESETSTATz goe high it has a 160uS period where it drops low.  Looking at the logic capture and identical timing characteristics it appears that ROM boot occurs twice.  Is this expected behavior?

I have captured the signals as you requested MCU_RESETSTATz drops low at the same moment as resetstatz, but the others remain unchanged.  I have also provided a couple of pages of the schematic that include power and reset to the processor.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1607595/am6421-resetstatz-output-during-rom-boot/6203293 

could you explain *what* you're booting? If this is e.g. U-Boot or a SBL with provisions for the i2368/i2331 errata, the bootloader will warm-reset the processor after the first boot, causing the ROM to load the bootloader image a second time. This also matches PORz_OUT remaining high, while RESETSTATz and MCU_RESETSTATz briefly go low.

this warm reset is implemented in the SBL, not in the ROM. You could check your own bootloader for this code sequence:

https://github.com/TexasInstruments/mcupsdk-core/blob/6a622a5c2729c5ad10ba066646944609dc0c64bb/examples/drivers/boot/sbl_ospi/am64x-evm/r5fss0-0_nortos/main.c#L71

The implementation for Bootloader_socResetWorkaround is here:

https://github.com/TexasInstruments/mcupsdk-core/blob/6a622a5c2729c5ad10ba066646944609dc0c64bb/source/drivers/bootloader/soc/am64x_am243x/bootloader_soc.c#L1249

If your application doesn't (and wont ever) use PRU-ICSSG or CPSW, I guess you could disable this code.

What happens is the boot ROM loads your code, the code detects the reset reason was a cold boot or a PORz, and executes a warm reset. Boot ROM loads your code for the second time, the reset reason is a warm boot, and your bootloader continues.

Regards,

Sreenivasa