TMS320C6678: C6678 SRIO read data 0xDEADDEAD

r-hishiki-uf

Part Number: TMS320C6678

Hi E2E Support

TMS320C6678 access and boot from Intel FPGA(Arria V SoC) using SRIO.

I verified boot magic address(0x1087FFFC) stored desired entry address(0x0C000000) and available access entry address(0x0C000000) using CCS memory dump,

but BOOTCOMPLETE register(0x0262013C) is all 0 and SRIO read data is already "0xDEADDEAD".

・What does "DEADDEADh" mean?

・How to set '1' bootcomplete register after writing boot magic address?

・What is condition to assert BOOTCOMPLETE pin(BOOTCOMPLETE register bit 'AND reduce')?

5 months ago

0 Shankari G 5 months ago

TI__Mastermind 22005 points

r-hishiki-uf,

Writing to the boot complete register is well demonstrated in the SRIO through put benchmark example of processor SDK 6.3

SrioDevice_init() function has all the details to initialize the peripheral. Please have a look at the demo code.

CSL_SRIO_GetBootComplete (hSrio, &bootCompleteFlag);

if (bootCompleteFlag == 1)
/* Set boot complete to be 0; to enable writing to the SRIO registers. */
CSL_SRIO_SetBootComplete (hSrio, 0);

Please follow the FAQ on how to run the SRIO through put benchmark example.

[FAQ] TMS320C6678: How to build and run the IPC-SRIO example on C6678 EVM? - Processors forum - Processors - TI E2E support forums

Other than this, we have many loop back examples for SRIO ( which encloses setting the boot complete register)

SRIO_Loopback_evmc6678_C66BiosTestProject

SRIO_LpbkDioIsr_evmc6678_C66BiosExampleProject

SRIO_MulticoreLpbk_evmc6678_C66BiosExampleProject

SRIO_TputBenchmarking_evmc6678_C66TestProject

Regards

Shankari G

0 r-hishiki-uf 5 months ago in reply to Shankari G

Prodigy 20 points

Shankari G,

Thanks for answers.

I thought BOOTCOMPLETE asserted by C6678 architecture automatically but I missed.

BOOTCOMPLETE register is set by firmware program, for example CSL_SRIO_SetBootComplete() function.

Please continue to answer following:

・What does "DEADDEADh" mean? →C6678 respons "DEADDEADh" until jump to Entry address?

・What is condition to assert BOOTCOMPLETE pin(BOOTCOMPLETE register bit 'AND reduce')?

Regards

+1 r-hishiki-uf 5 months ago in reply to r-hishiki-uf

Prodigy 20 points

Shankari G,

・What does "DEADDEADh" mean? →C6678 respons "DEADDEADh" until jump to Entry address?

It turns out "DEADDEADh" data is created by intel fpga IP core interconnect in more servey. I'm sorry I was wrong.

0 Shankari G 5 months ago in reply to r-hishiki-uf

TI__Mastermind 22005 points

r-hishiki-uf

Sure.

Your Question:-

r-hishiki-uf said:
・What is condition to assert BOOTCOMPLETE pin(BOOTCOMPLETE register bit 'AND reduce')?

Answer:-

The RBL uses the BOOTCOMPLETE register, which controls the BOOTCOMPLETE pin status, to indicate the completion of the RBL boot process. The BOOTCOMPLETE pin goes high when the boot complete bits in the BOOTCOMPLETE register for all the cores are set. The RBL sets the bits for each CorePac once it completes the boot process in the CorePac and just before it exits the process. Because of legacy implementation, the BOOTCOMPLETE bit in the register corresponding to the CorePac0 is set by the hardware.

Question :-

r-hishiki-uf said:
What does "DEADDEADh" mean? →C6678 respons "DEADDEADh" until jump to Entry address?

Answer:-

May be some invalid default value. i.e., 0xDEADDEAD Hex value--> For example, i.e., the Binary Value --> 1101 1110 1010 1101 1101 1110 1010 1101

By the way what is the address in which this hex value is stored? which you did the SRIO read...

Regards

Shankari G