AM623: emmc error

Hi Li,

I see you kernel device tree has "no-1-8-v;" on &sdhci1 node. Can you please add the same to &sdhci0 node to see if the eMMC error still happens?

I added no-1-8-v to&sdhci0, the eMMC error still happens

During multiple repeated reboot tests, there may occasionally be one or two occurrences of the emmc error mentioned above
The logs with errors during testing are as follows：

emmc-log.txt

Simultaneously conducting another test, frequent read operations (2ms interval) on the RPMB partition of EMMC will result in the following errors

Hi Li,

With 'no-1-8-v' configuration, the Linux log shows eMMC is enumerated in High Speed mode, but Linux still has this access error.

I am routing your query to our MMC hardware expert for comments on hardware design related factors.

Hi Liu,
Has the TI expert responded to this question yet？

It is not clear if you are having problems with read or write operations. I suggest you perform some tests where you write data patterns into the eMMC device at the slower transfer rate, then try to read same data back at the higher transfer rate and compare the data patterns. This should help identify if you are having problems with reads or writes.

Did you design your PCB to be compliant with the parameters defined in the Timing Conditions table found in the HS200 timing section of the datasheet?

Have you checked the timing relationship of clock to data during read transactions?  Did you check the signal quality of the signals during read and write transactions to ensure that are no unexpected signal distortion at the respective receiver?

Regards,
Paul

Hi Liu，
I found a similar issue post on the forum, which shows that there is currently no solution on the Linux 5.10.168 kernel, and this issue will be resolved later？

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1327667/am625-emmc-tranision-issue/5104521?tisearch=e2e-sitesearch&keymatch=emmc%252525252525252520stress%252525252525252520test#5104521

"It is not clear if you are having problems with read or write operations. I suggest you perform some tests where you write data patterns into the eMMC device at the slower transfer rate, then try to read same data back at the higher transfer rate and compare the data patterns. This should help identify if you are having problems with reads or writes."

At the same time, I saw Paul proposing to write emmc at a lower speed and then read emmc at a higher speed. May I ask if TI has a corresponding testing method? How to make the reading and writing speed different？

Regards,
LI

Hi Paul,

After multiple reboots, I encountered an error as shown in the log below：

[com COM14] (2024-03-26_183038) COM14 (Prolific PL2303GC USB Serial COM Port (COM14)).log

After an error occurred in the EMMC, I measured the CLK clock with an oscilloscope to be 400Khz, and there is no data transfer on data0，as shown in the following figure：

In the absence of any errors in EMMC, the waveforms of CMD and data0 are as follows：

Our PCB related settings are shown in the following figure：

At the same time, I used the following shell script for stress testing, and after a day of testing, I did not find any errors in EMMC：

#!/bin/bash

emmc_stress_test() {

    TEST_FILE="/run/media/mmcblk0p13/test_file"
    TEST_DATA_SIZE="100M"

    WRITE_BS="1M"
    WRITE_COUNT=104

    READ_BS_HS200="2M"
    READ_COUNT_HS200=100

    READ_BS_HS400="4M"
    READ_COUNT_HS400=100

    dd if=/dev/zero of="$TEST_FILE" bs=$WRITE_BS count=$WRITE_COUNT conv=fsync
    dd if="$TEST_FILE" of=/dev/null bs=$READ_BS_HS200 count=$READ_COUNT_HS200
    dd if="$TEST_FILE" of=/dev/null bs=$READ_BS_HS400 count=$READ_COUNT_HS400
    rm -f "$TEST_FILE"
}

while true; do
    emmc_stress_test
    sleep 0.001
done

Let me make sure I understand the issue.

Are you saying the system occasionally experiences a boot failure, but you never encounter any errors if you perform a stress test after a good boot?

Are you waiting long enough for all power rails to decay below 0.3V before turning power back on after it was turned off?

Does your system provide a hardware reset to the eMMC device to ensure it is in a known state before boot begins?  If so, have you confirmed the eMMC device has been released from reset long enough before it is accessed during boot?

I can only suggest you look very carefully at all start-up conditions and compare the state of power rails and signals for the working case vs the none working case.

Regards,
Paul

Hi Li,

li weiyu said:

I found a similar issue post on the forum, which shows that there is currently no solution on the Linux 5.10.168 kernel, and this issue will be resolved later？

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1327667/am625-emmc-tranision-issue/5104521?tisearch=e2e-sitesearch&keymatch=emmc%252525252525252520stress%252525252525252520test#5104521

Actually I just replied to this very E2E thread that you found earlier today, please see my latest post here https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1327667/am625-emmc-tranision-issue/5128775#5128775 

There I'm asking to run an experiment of using our latest kernel tree (v6.1-based) _plus_ an extra patch that is required to properly enable the ITAPDLY eMMC calibration feature, which is all described in https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1344972/am623-issues-with-sandisk-emmc-entering-hs200-mode/5124827#5124827

Even you are on Kernel v5.x it is important in such cases to at least try the latest software stack due to the complex nature of the drivers and the overall setup. And in case the latest software stack works we can then always look for ways to back-port specific changes to your environment in case you must use kernel v5.x. But that's a second step. First, let's try to find something that works reliably.

Regards, Andreas