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AM62A7-Q1: CPSW loopback CPPI receive data, but DMA is empty

Herry Huang
Prodigy 40 points
Part Number: AM62A7-Q1

Hi Expert

     Now we have AM62 for BBU, i set to loopback mode to verify board is OK, beacuse CPPI can got data, but RINGCC is empty.

     RGMII port1 send OK, 0x803a234 is 0x1, 0x803a264 is 0x40,  at same time , CPPI port0 got same frame and bytes. 0x803a000 is 0x1, 0x803a230 is 0x40,  so why RINGCC is empty? occupy flash always 0.

     Thanks

     

    

  • +1
    TI__Mastermind 22940 points

    Hi Harry,

    The data flow in CPSW is as follows.

    Internal cores Tx -> CPPI Port Rx -> External Port to Network via PHY or switch i.e. External Port Tx.
    In above from CPPI port to external port will be as directed packet or based on ALE rules and packet match will transfer to External Port Tx FIFO. 

    If you enabled loopback at PHY.
    PHY loopback -> External Port Rx -> CPPI Port to Internal cores i.e. CPPI Tx.
    In above from external Port to CPPI Port will be based on ALE rules and packet match or Port is in promisc mode (MAN only Port Mode).

    Please check CPSW statistics as per above, if statistics are increasing as per above then only you will receive the packets.
    From above CPSW statistics dump I could not see any External Port Rx count So, there is no data received by CPSW and forwarded to Internal cores.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hi Sudheer

         Thank you , i got it , i will ask HW engineer assist me to find out the problem.

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hi Sudheer

         I think that problem maybe about timing. Now DP83TG720 work at align mode, so CPSW i set to no delay mode in driver, so i set phy-more as rgmii replace rgmii-rxid. But strangn thing is PCS loopbakc no RX data anymore.

         My question is

         1: How to confirm problem is timing?  

         2: Why PCS loopback no RX data send out?

         Thanks

  • 0 in reply to Herry Huang
    TI__Mastermind 34815 points

    Hi,

    Could you please summarize where you made changes to the driver in U-Boot? 

    For RGMII typically the MAC has a 2nS delay configured automatically on the TX and it is expected that the PHY will add 2nS of delay on the RX path. So rgmii-rxid is required. Additional timing adjustments maybe required based on the layout. Typically the PHY timing changes are made in the DTS file, this is the case for Linux anyway.

    Best Regards,

    Schuyler

  • 0 in reply to Schuyler Patton
    Prodigy 40 points

    Hi Schuyler

         yes ,due to phy is at algin mode, so i set to rgmii

         

         At same time, i add rgmii delay, but default is 0

         

         And waveform like this

         

  • 0 in reply to Herry Huang
    Prodigy 40 points

    Hi Schuyler

         I set dp83tg720 to mii loopback mode, finally i receive alignment error frame. so how to adjuct the delay value？ thanks

         

  • 0 in reply to Herry Huang
    Prodigy 40 points

    Hi Schuyler

         I resolved this issue,  the reason is RGMII timing, due to our phy is align mode, so TX & RX need set to shift mode, enable phy internal delay at same time.