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TDA4VM: R5F Data cache activation process

idont know
Prodigy 20 points
Part Number: TDA4VM

hello TI support.

I am currently working on a baremetal environnement on TDA4VM processor.

i am trying to enable the data cache for the R5F on the MCU domain.

i see in the documentation that i need to set to 1 the bit number 2 of the SCTLR register.

but at the moment that i write on this bit the r5 core is not reponding anymore .

is there a procedure that i need to do before this operation ?

thank you in advance.

  • 0
    TI__Guru* 80495 points

    Hello,

    Are you not using the RTOS PDK startup code? Are you writing your own software completely from scratch? 

    regards

    Suman

  • 0 in reply to Suman Anna
    Prodigy 20 points

    hello suman,

    i am currently develloping on my own software.

    i try to enable the d cache in ASM and i think that i nned a process before the activation, because the core is not working at the exact moment that i activate the d cache.

  • 0 in reply to idont know
    TI__Guru* 80495 points

    Hello,

    R5F startup sequence should be a standard ARM R5F sequence, so you would have to follow those. This is outside of our support scope.

    I can only provide a reference to our startup code, that you can refer to and figure out your custom sequence.

    There is code in our PDK CSL code for startup sequence, and the overall sequence will have been executed in any of our PDK baremetal examples.

    Please see various files in the <RTOS SDK>/<PDK>/packages/ti/csl/arch/r5/src/startup folder, primarily the startup.c and r5_startup.asm files.

    I recommend that you run one of our samples on the EVM to understand the boot-up sequence.

    regards

    Suman