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TDA4VH-Q1: Consult how to realize the safety mechanism of DDR9 write/read for DDR module according to safety manual

Donghua Ni
Prodigy 20 points
Part Number: TDA4VH-Q1

Hello TI expert,

Regarding the safety mechanism of DDR9 write/read, we have some questions with how to realize it:

We know that the SM could be realized eith at Main domain A core or at MCU domain, and it can be executed at boot or peridically.

Our design configuration: 4 pcs 2G DDR, and now we set the monitor size of 64*1024bit for each piece DDR.

Question1: If we the SM is realized at Main domain, in order to achive a high diagnosis coverage, how many size space should be monitored according to your experience? And if you have any suggestions for the selected address area?

Question2: If we the SM is realized at MCU domain, in order to achive a high diagnosis coverage, how many size space should be monitored according to your experience? And if you have any suggestions for the selected address area?

Question3: we learned that the DDR9 is worked at interleaver model, when one fault is qulified, we don't know which piece DDR of the fault was from, my I ask is it sure? If yes, do you have any measure to solve this issue?

FYI: the sreenshort of DDR9 from safety manual.

Thanks in advance.

  • 0
    TI__Genius 16250 points

    Hi,

    Regarding DDR9, the safety Manual offers the below, where, expectation would be that once DDR it initialized a small write/read to DDR to ensure it is functional could be done.  Note that the below documentation indicates that periodic checking is not required.

    In systems targeting 90% diagnostic coverage the system integrator shall implement the following diagnostic group -
    •     DDR.Diags - This diagnostic option contains DDR9, DDR11, DDR12, DDR15, DDR16, DDR-T5, DDR-T6, CBA1, CBA2, CBA3, CLK5A, CLK5B, CLK5C

    99% diagnostic coverage is currently not being claimed for this IP. It provides coverage for latent faults. but no coverage for permanent/transient fault.

    Regards,

    Josiitaa

  • 0 in reply to Josiitaa RL
    Prodigy 20 points

    Hello,

    Thanks for your reply, regarding the small write/read to DDR even at initialization phase, how many space is proper based on your experience or field experience from other customer?

    And what about the quesiont 3?

  • 0 in reply to Donghua Ni
    TI__Genius 16250 points

    Hi,

    I will have to check internally. I will get back to you.

    Regards,

    Josiitaa

  • 0 in reply to Josiitaa RL
    Prodigy 20 points

    Thank for your check. Is there any progress for this topic.

  • 0 in reply to Donghua Ni
    TI__Genius 16250 points

    Hi,

    We do not have a suggestion for the space to be allocated as that would depend on the application use case.

    Donghua Ni said:
    Question3: we learned that the DDR9 is worked at interleaver model, when one fault is qulified, we don't know which piece DDR of the fault was from, my I ask is it sure? If yes, do you have any measure to solve this issue?

    I am not sure I understand the question here. The fault address would correspond to the injection bit value and memory address. So you will be able to identify the DDR address region.

    Regards,

    Josiitaa

  • 0 in reply to Josiitaa RL
    Prodigy 20 points

    Hello,

    Ok, if you don't have any proposal , then we will decide it based on our use case.

    Thanks.