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TMS320VC5509A: CLKIN and McBSP output clock signal timing

Part Number: TMS320VC5509A

Hi Experts,

Please tell me about the relationship between CLKIN and McBSP output clock(CLKX) in TMS320VC5509A.
CPU CLOCK is generated by multiplying CLKIN by 4 using the internal PLL.
McBSP's output clock (CLKX) is generated by McBSP's Sample Rate Generator, which divides the CPU CLOCK.

Is it possible to set the CLKX edge timing and CLKIN edge timing to the same position every time even after resetting?

When using 5509A, there is a timing that matches the CPU CLOCK multiplier.
But using 5409, the timing of CLKIN and BCLKX(Equivalent to CLKX of 5509A) is always constant. (Independent of multiplier)

Best regards,

  • Hello,

    Unfortunately, the expert that can help with this question is out of office until next week. The response may be delayed until then. Apologies for the inconvenience

     

    Best,

    Daniel

  • Hi There,

    According to the following diagram, the CLKIN is the input clock for the DPLL of DSP CLOCK Generator (see the answer to your other post):

    CLKX is the transmit sample rate clock for McBSP. It is controlled by the register CLKGDV. I do not see any register to control the edge timing.

       

    Since the sample rate clock is simply the division of the CPU clock, I do not think the jitter is from the McBSP. It must be in the DPLL of the DSP Clock Generator.

    Best regards,

    Ming

  • Hi Ming,

    I'm also looking at that documents.
    We changed the board design because 5409 and other parts were EOL.
    When measuring the waveform before and after change, there was a difference in clock timing.
    But, I don't know the reason for the 5409 timing.

    I wanted to ask if it is possible to set the 5509A to the same timing as the 5409.
    Looking at the answers, I thought it wasn't possible to configure it.

    Thank you.

  • Hi,

    You are correct. I do not see a way to change the McBSP edge timing on C5509A.

    Best regards, 

    Ming