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DRA821U-Q1: power consumption and USB, Ethernet port

Part Number: DRA821U-Q1
Other Parts Discussed in Thread: DRA821

Q1: what is the sleep current of DRA821U2-Q1 with 8GB DDR SRAM and 64MB SPI flash ?

Q2: Can you help to confirm if DRA821U2-Q1 ethernet ports support VLAN port tagging?

Q3: DRA821U2-Q1 has USB 3.1, is this USB secure for diagnostic and data retrieval?

Thanks

Max

  • Hi,

    Q1: what is the sleep current of DRA821U2-Q1 with 8GB DDR SRAM and 64MB SPI flash ?

    When you say sleep current, what is the SOC state? Can you elaborate more?

    - Keerthy

  • Sleep: lowest power consumption, it can be waked by ethernet or CAN, SOC should be in low power mode.

    do you have reference number for DRA821U2-Q1 subsystem (8GB DDR, 64MB NOR, 32GB eMMC) power consumption?

    I am looking for sleep current at the moment, you may have different modes, but I am looking for lowest consumption to meet customer requirement.

    Thanks

    Max

  • Max,

    The lowest power scenario for the SoC is "IO retention" mode.  In this mode all rails of the SoC are powered down except for the IO rails (3.3V or 1.8V depending on the system requirements).  In this mode, the IOs can detect a "wake event' (say from CAN) and trigger the external PMIC to power-on SoC rails and resume normal operation.  While in IO retention the SoC is expected to consume <5mA.

    Regards,

    Kyle

  • Our customer is asking for 200uA - 300uA, it is not posssible for DRA821 system, right?

  • Max,

    You could completely power down the SoC and use some GPIO to trigger the PMIC to power-up and the SoC can resume operation (reboot).  This would completely eliminate any power from the SoC.

    Regards,

    Kyle