PROCESSOR-SDK-AM62A: AM6254ATCGHAALW , phyCORE-AM62Ax

Hello,

I'm currently investigating the possibility of changing the C7x DSP core L2 SRAM to cache on the AM62Ax processor. Do you know if this is possible and if there are any examples available in CCS demonstrating how to achieve this?

I've found some suggestions on E2E forums that for products with a similar structure and featuring the C7x, it might be possible to make this change by increasing the cache size and configuring MMU page tables. Would this be the correct strategy for the AM62Ax?

Within the DSP examples (located under the /source folder), there are some APIs (e.g., FFTLIB_TEST_c7xSetL2CC) for setting L2 cache registers. However, it seems that these APIs haven't been utilized in the AM62Ax SDK, and there are TODO comments in the code (e.g., TI_cache.c):

/* TODO: Configure DSP L1 and L2 cache registers, and call TI_meminit() */
/*       Check c6x implementation                                       */
int32_t TI_cache_init (void) { return (0); }