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[FAQ] TDA4VM: Issues with Cascaded Timer feature

Parth Nagpal
Mastermind 42125 points
Part Number: TDA4VM

Tool/software:

Hi,

The timer module in TDA4x devices provides an option to cascade the timers. Each odd numbered timer instance from each of the domain may be optionally cascaded with previous even numbered timer instance for the same domain to form up to a 64-bit timer.  When cascaded, TIMER_i acts as a 32- bit pre scaler to TIMER_1+1

I am trying to implement the feature with the below implementation:

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <stdint.h>
#include <ti/board/board.h>
 
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
 
#include <ti/csl/cslr.h>
 
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
#define CTRL_MMR_CAP_SEL 0x40F04204
#define TIMER2_TLDR 0x40410040
#define TIMER2_TWPS 0x40410048
#define TIMER2_TCLR 0x40410038
#define TIMER2_TTGR 0x40410044
#define TIMER2_TCRR 0x4041003C
 
#define TIMER1_TLDR 0x40400040
#define TIMER1_TWPS 0x40400048
#define TIMER1_TTGR 0x40400044
#define TIMER1_TCLR 0x40400038
#define TIMER1_TCRR 0x4040003C
 
 
 
/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
 
 
//Timer 2 should start counting when timer 1 overflows
int main(void)
{
    Board_initCfg           boardCfg;
 
    boardCfg = BOARD_INIT_UNLOCK_MMR    |
           BOARD_INIT_MODULE_CLOCK  |
               BOARD_INIT_PINMUX_CONFIG |
               BOARD_INIT_UART_STDIO;
    Board_init(boardCfg);
     
    volatile uint32_t twps_val = 1;
    volatile uint32_t timer2;
    volatile uint32_t timer1;
 
    UART_printf("Cascaded Timer Test\n");
    UART_printf("Enabling Cascade\n");
    CSL_REG32_WR(CTRL_MMR_CAP_SEL, 0x100);
     
 
    UART_printf("Setting up timer 2\n"); 
    CSL_REG32_WR(TIMER2_TLDR, 0xFFFFFFF0);
 
    CSL_REG32_WR(TIMER2_TTGR, 0x20);
    CSL_REG32_WR(TIMER2_TCLR, 0x1);
 
    UART_printf("Checking write posted for TCLR2\n");
    twps_val = CSL_REG32_RD(TIMER2_TWPS);
    while(twps_val == 0x1)
    {
    twps_val = CSL_REG32_RD(TIMER2_TWPS);
    }
 
 
    UART_printf("Setting up timer 1\n");
    CSL_REG32_WR(TIMER1_TLDR, 0xF0000000);
     
    CSL_REG32_WR(TIMER1_TTGR, 0x20);
    CSL_REG32_WR(TIMER1_TCLR, 0x403);
  
    UART_printf("Checking TWPS Val\n");
  
    while(twps_val == 0x1)
    {
     twps_val = CSL_REG32_RD(TIMER1_TWPS);
    }
 
    while(1)
    {
      timer1 = CSL_REG32_RD(TIMER1_TCRR);
      timer2 = CSL_REG32_RD(TIMER2_TCRR);
      UART_printf("TIMER1 = 0x%x, TIMER2 = 0x%x\n", timer1, timer2);
    }
     
    return(0);
}

Please see the logs attached from the above code.

SBL Revision: 01.00.10.01 (Jul 27 2023 - 17:57:55)
TIFS  ver: 9.0.6--v09.00.06 (Kool Koala)
Cascaded Timer Test
Enabling Cascade
Setting up timer 2
Checking write posted for TCLR2
Setting up timer 1
Checking TWPS Val
TIMER1 = 0xf04c63f3, TIMER2 = 0x0
TIMER1 = 0xf0d5ecef, TIMER2 = 0x0
TIMER1 = 0xf15f6e23, TIMER2 = 0x0
TIMER1 = 0xf1e8ef45, TIMER2 = 0x0
TIMER1 = 0xf272706d, TIMER2 = 0x0
TIMER1 = 0xf2fbf18f, TIMER2 = 0x0
TIMER1 = 0xf38572b7, TIMER2 = 0x0
TIMER1 = 0xf40ef3df, TIMER2 = 0x0
TIMER1 = 0xf4987501, TIMER2 = 0x0
TIMER1 = 0xf521f623, TIMER2 = 0x0
TIMER1 = 0xf5ab7751, TIMER2 = 0x0
TIMER1 = 0xf634f879, TIMER2 = 0x0
TIMER1 = 0xf6be79a1, TIMER2 = 0x0
TIMER1 = 0xf747fac3, TIMER2 = 0x0
TIMER1 = 0xf7d17beb, TIMER2 = 0x0
TIMER1 = 0xf85afd19, TIMER2 = 0x0
TIMER1 = 0xf8e47e41, TIMER2 = 0x0
TIMER1 = 0xf96dff63, TIMER2 = 0x0
TIMER1 = 0xf9f7808b, TIMER2 = 0x0
TIMER1 = 0xfa8101a7, TIMER2 = 0x0
TIMER1 = 0xfb0a82c9, TIMER2 = 0x0
TIMER1 = 0xfb9403f1, TIMER2 = 0x0
TIMER1 = 0xfc1d8519, TIMER2 = 0x0
TIMER1 = 0xfca70641, TIMER2 = 0x0
TIMER1 = 0xfd308769, TIMER2 = 0x0
TIMER1 = 0xfdba0897, TIMER2 = 0x0
TIMER1 = 0xfe4389b9, TIMER2 = 0x0
TIMER1 = 0xfecd0ae1, TIMER2 = 0x0
TIMER1 = 0xff568c03, TIMER2 = 0x0
TIMER1 = 0xffe00d37, TIMER2 = 0x0
TIMER1 = 0xf0698e65, TIMER2 = 0x0  --------------------> 1st OverFlow
TIMER1 = 0xf0f30f93, TIMER2 = 0x0
TIMER1 = 0xf17c90bb, TIMER2 = 0x0
TIMER1 = 0xf20611e9, TIMER2 = 0x0
TIMER1 = 0xf28f9317, TIMER2 = 0x0
TIMER1 = 0xf319143f, TIMER2 = 0x0
TIMER1 = 0xf3a29567, TIMER2 = 0x0
TIMER1 = 0xf42c168f, TIMER2 = 0x0
TIMER1 = 0xf4b597b1, TIMER2 = 0x0
TIMER1 = 0xf53f18df, TIMER2 = 0x0
TIMER1 = 0xf5c89a07, TIMER2 = 0x0
TIMER1 = 0xf6521b29, TIMER2 = 0x0
TIMER1 = 0xf6db9c51, TIMER2 = 0x0
TIMER1 = 0xf7651d73, TIMER2 = 0x0
TIMER1 = 0xf7ee9e9b, TIMER2 = 0x0
TIMER1 = 0xf8781fc3, TIMER2 = 0x0
TIMER1 = 0xf901a0e5, TIMER2 = 0x0
TIMER1 = 0xf98b2207, TIMER2 = 0x0
TIMER1 = 0xfa14a335, TIMER2 = 0x0
TIMER1 = 0xfa9e245d, TIMER2 = 0x0
TIMER1 = 0xfb27a585, TIMER2 = 0x0
TIMER1 = 0xfbb126a7, TIMER2 = 0x0
TIMER1 = 0xfc3aa7cf, TIMER2 = 0x0
TIMER1 = 0xfcc428fd, TIMER2 = 0x0
TIMER1 = 0xfd4daa25, TIMER2 = 0x0
TIMER1 = 0xfdd72b47, TIMER2 = 0x0
TIMER1 = 0xfe60ac6f, TIMER2 = 0x0
TIMER1 = 0xfeea2d8b, TIMER2 = 0x0
TIMER1 = 0xff73aead, TIMER2 = 0x0
TIMER1 = 0xfffd2fd5, TIMER2 = 0x0
TIMER1 = 0xf086b0fd, TIMER2 = 0x0  --------------------> 2nd OverFlow
TIMER1 = 0xf1103225, TIMER2 = 0x0
TIMER1 = 0xf199b34d, TIMER2 = 0x0
TIMER1 = 0xf223347b, TIMER2 = 0x0
TIMER1 = 0xf2acb59d, TIMER2 = 0x0
TIMER1 = 0xf33636c5, TIMER2 = 0x0
TIMER1 = 0xf3bfb7f3, TIMER2 = 0x0
TIMER1 = 0xf449391b, TIMER2 = 0x0
TIMER1 = 0xf4d2ba49, TIMER2 = 0x0
TIMER1 = 0xf55c3b77, TIMER2 = 0x0
TIMER1 = 0xf5e5bc9f, TIMER2 = 0x0
TIMER1 = 0xf66f3dc7, TIMER2 = 0x0
TIMER1 = 0xf6f8beef, TIMER2 = 0x0
TIMER1 = 0xf7824011, TIMER2 = 0x0
TIMER1 = 0xf80bc13f, TIMER2 = 0x0
TIMER1 = 0xf8954267, TIMER2 = 0x0
TIMER1 = 0xf91ec389, TIMER2 = 0x0
TIMER1 = 0xf9a844b1, TIMER2 = 0x0
TIMER1 = 0xfa31c5d3, TIMER2 = 0x0
TIMER1 = 0xfabb46fb, TIMER2 = 0x0
TIMER1 = 0xfb44c823, TIMER2 = 0x0
TIMER1 = 0xfbce4945, TIMER2 = 0x0
TIMER1 = 0xfc57ca67, TIMER2 = 0x0
TIMER1 = 0xfce14b95, TIMER2 = 0x0
TIMER1 = 0xfd6accbd, TIMER2 = 0x0
TIMER1 = 0xfdf44de5, TIMER2 = 0x0
TIMER1 = 0xfe7dcf07, TIMER2 = 0x0
TIMER1 = 0xff07502f, TIMER2 = 0x0
TIMER1 = 0xff90d15d, TIMER2 = 0x0
TIMER1 = 0xf01a5285, TIMER2 = 0x0  --------------------> 3rd OverFlow
TIMER1 = 0xf0a3d3a7, TIMER2 = 0x0
TIMER1 = 0xf12d54cf, TIMER2 = 0x0
TIMER1 = 0xf1b6d5eb, TIMER2 = 0x0
TIMER1 = 0xf2405719, TIMER2 = 0x0
TIMER1 = 0xf2c9d83b, TIMER2 = 0x0
TIMER1 = 0xf3535963, TIMER2 = 0x0
TIMER1 = 0xf3dcda85, TIMER2 = 0x0
TIMER1 = 0xf4665bad, TIMER2 = 0x0
TIMER1 = 0xf4efdcdb, TIMER2 = 0x0
TIMER1 = 0xf5795dfd, TIMER2 = 0x0
TIMER1 = 0xf602df25, TIMER2 = 0x0
TIMER1 = 0xf68c6047, TIMER2 = 0x0
TIMER1 = 0xf715e17b, TIMER2 = 0x0
TIMER1 = 0xf79f62a3, TIMER2 = 0x0
TIMER1 = 0xf828e3c5, TIMER2 = 0x0
TIMER1 = 0xf8b264ed, TIMER2 = 0x0
TIMER1 = 0xf93be609, TIMER2 = 0x0
TIMER1 = 0xf9c5672b, TIMER2 = 0x0
TIMER1 = 0xfa4ee853, TIMER2 = 0x0
TIMER1 = 0xfad8697b, TIMER2 = 0x0
TIMER1 = 0xfb61ea9d, TIMER2 = 0x0
TIMER1 = 0xfbeb6bcb, TIMER2 = 0x0
TIMER1 = 0xfc74ecf3, TIMER2 = 0x0
TIMER1 = 0xfcfe6e1b, TIMER2 = 0x0
TIMER1 = 0xfd87ef43, TIMER2 = 0x0
TIMER1 = 0xfe117071, TIMER2 = 0x0
TIMER1 = 0xfe9af199, TIMER2 = 0x0
TIMER1 = 0xff2472c7, TIMER2 = 0x0
TIMER1 = 0xffadf3f5, TIMER2 = 0x0
TIMER1 = 0xf037751d, TIMER2 = 0x0  --------------------> 4th OverFlow
TIMER1 = 0xf0c0f645, TIMER2 = 0x0
TIMER1 = 0xf14a7767, TIMER2 = 0x0
TIMER1 = 0xf1d3f88f, TIMER2 = 0x0
TIMER1 = 0xf25d79bd, TIMER2 = 0x0
TIMER1 = 0xf2e6fae5, TIMER2 = 0x0
TIMER1 = 0xf3707c0d, TIMER2 = 0x0
TIMER1 = 0xf3f9fd2f, TIMER2 = 0x0
TIMER1 = 0xf4837e5d, TIMER2 = 0x0
TIMER1 = 0xf50cff7f, TIMER2 = 0x0
TIMER1 = 0xf59680a7, TIMER2 = 0x0
TIMER1 = 0xf62001cf, TIMER2 = 0x0
TIMER1 = 0xf6a982f1, TIMER2 = 0x0
TIMER1 = 0xf7330419, TIMER2 = 0x0
TIMER1 = 0xf7bc8541, TIMER2 = 0x0
TIMER1 = 0xf8460669, TIMER2 = 0x0
TIMER1 = 0xf8cf8791, TIMER2 = 0x0
TIMER1 = 0xf95908bf, TIMER2 = 0x0
TIMER1 = 0xf9e289e1, TIMER2 = 0x0
TIMER1 = 0xfa6c0b09, TIMER2 = 0x0
TIMER1 = 0xfaf58c37, TIMER2 = 0x0
TIMER1 = 0xfb7f0d5f, TIMER2 = 0x0
TIMER1 = 0xfc088e87, TIMER2 = 0x0
TIMER1 = 0xfc920faf, TIMER2 = 0x0
TIMER1 = 0xfd1b90d1, TIMER2 = 0x0
TIMER1 = 0xfda511ff, TIMER2 = 0x0
TIMER1 = 0xfe2e9327, TIMER2 = 0x0
TIMER1 = 0xfeb81449, TIMER2 = 0x0
TIMER1 = 0xff419571, TIMER2 = 0x0
TIMER1 = 0xffcb1693, TIMER2 = 0x0
TIMER1 = 0xf05497bb, TIMER2 = 0x0  --------------------> 5th OverFlow
TIMER1 = 0xf0de18e3, TIMER2 = 0x0
TIMER1 = 0xf1679a05, TIMER2 = 0x0
TIMER1 = 0xf1f11b33, TIMER2 = 0x0
TIMER1 = 0xf27a9c5b, TIMER2 = 0x0
TIMER1 = 0xf3041d83, TIMER2 = 0x0
TIMER1 = 0xf38d9eab, TIMER2 = 0x0
TIMER1 = 0xf4171fd9, TIMER2 = 0x0
TIMER1 = 0xf4a0a101, TIMER2 = 0x0
TIMER1 = 0xf52a2229, TIMER2 = 0x0
TIMER1 = 0xf5b3a34b, TIMER2 = 0x0
TIMER1 = 0xf63d2473, TIMER2 = 0x0
TIMER1 = 0xf6c6a5a1, TIMER2 = 0x0
TIMER1 = 0xf75026c9, TIMER2 = 0x0
TIMER1 = 0xf7d9a7eb, TIMER2 = 0x0
TIMER1 = 0xf8632913, TIMER2 = 0x0
TIMER1 = 0xf8ecaa2f, TIMER2 = 0x0
TIMER1 = 0xf9762b5d, TIMER2 = 0x0
TIMER1 = 0xf9ffac7f, TIMER2 = 0x0
TIMER1 = 0xfa892da7, TIMER2 = 0x0
TIMER1 = 0xfb12aec9, TIMER2 = 0x0
TIMER1 = 0xfb9c2ff1, TIMER2 = 0x0
TIMER1 = 0xfc25b11f, TIMER2 = 0x0
TIMER1 = 0xfcaf3241, TIMER2 = 0x0
TIMER1 = 0xfd38b369, TIMER2 = 0x0
TIMER1 = 0xfdc2348b, TIMER2 = 0x0
TIMER1 = 0xfe4bb5bf, TIMER2 = 0x0
TIMER1 = 0xfed536e7, TIMER2 = 0x0
TIMER1 = 0xff5eb809, TIMER2 = 0x0
TIMER1 = 0xffe83931, TIMER2 = 0x0
TIMER1 = 0xf071ba4d, TIMER2 = 0x1  --------------------> 6th OverFlow
TIMER1 = 0xf0fb3b6f, TIMER2 = 0x1
TIMER1 = 0xf184bc97, TIMER2 = 0x1
TIMER1 = 0xf20e3dbf, TIMER2 = 0x1
TIMER1 = 0xf297bee1, TIMER2 = 0x1
TIMER1 = 0xf321400f, TIMER2 = 0x1
TIMER1 = 0xf3aac137, TIMER2 = 0x1
TIMER1 = 0xf434425f, TIMER2 = 0x1
TIMER1 = 0xf4bdc387, TIMER2 = 0x1
TIMER1 = 0xf54744a9, TIMER2 = 0x1
TIMER1 = 0xf5d0c5dd, TIMER2 = 0x1
TIMER1 = 0xf65a4705, TIMER2 = 0x1
TIMER1 = 0xf6e3c827, TIMER2 = 0x1
TIMER1 = 0xf76d494f, TIMER2 = 0x1
TIMER1 = 0xf7f6ca7d, TIMER2 = 0x1
TIMER1 = 0xf8804ba5, TIMER2 = 0x1
TIMER1 = 0xf909ccc7, TIMER2 = 0x1
TIMER1 = 0xf9934def, TIMER2 = 0x1
TIMER1 = 0xfa1ccf0b, TIMER2 = 0x1
TIMER1 = 0xfaa65039, TIMER2 = 0x1
TIMER1 = 0xfb2fd15b, TIMER2 = 0x1
TIMER1 = 0xfbb95283, TIMER2 = 0x1
TIMER1 = 0xfc42d3b1, TIMER2 = 0x1
TIMER1 = 0xfccc54d9, TIMER2 = 0x1
TIMER1 = 0xfd55d601, TIMER2 = 0x1
TIMER1 = 0xfddf5729, TIMER2 = 0x1
TIMER1 = 0xfe68d851, TIMER2 = 0x1
TIMER1 = 0xfef2597f, TIMER2 = 0x1
TIMER1 = 0xff7bdaa1, TIMER2 = 0x1
TIMER1 = 0xf0055bc9, TIMER2 = 0x1  --------------------> 7th OverFlow
TIMER1 = 0xf08edceb, TIMER2 = 0x1
TIMER1 = 0xf1185e1f, TIMER2 = 0x1
TIMER1 = 0xf1a1df47, TIMER2 = 0x1
TIMER1 = 0xf22b606f, TIMER2 = 0x1
TIMER1 = 0xf2b4e191, TIMER2 = 0x1
TIMER1 = 0xf33e62bf, TIMER2 = 0x1
TIMER1 = 0xf3c7e3e7, TIMER2 = 0x1
TIMER1 = 0xf4516509, TIMER2 = 0x1
TIMER1 = 0xf4dae631, TIMER2 = 0x1
TIMER1 = 0xf5646753, TIMER2 = 0x1
TIMER1 = 0xf5ede87b, TIMER2 = 0x1
TIMER1 = 0xf67769a3, TIMER2 = 0x1
TIMER1 = 0xf700eac5, TIMER2 = 0x1
TIMER1 = 0xf78a6bf3, TIMER2 = 0x1
TIMER1 = 0xf813ed1b, TIMER2 = 0x1
TIMER1 = 0xf89d6e43, TIMER2 = 0x1
TIMER1 = 0xf926ef6b, TIMER2 = 0x1
TIMER1 = 0xf9b0708d, TIMER2 = 0x1
TIMER1 = 0xfa39f1a9, TIMER2 = 0x1
TIMER1 = 0xfac372cb, TIMER2 = 0x1
TIMER1 = 0xfb4cf3e7, TIMER2 = 0x1
TIMER1 = 0xfbd67515, TIMER2 = 0x1
TIMER1 = 0xfc5ff637, TIMER2 = 0x1
TIMER1 = 0xfce9775f, TIMER2 = 0x1
TIMER1 = 0xfd72f88d, TIMER2 = 0x1
TIMER1 = 0xfdfc79b5, TIMER2 = 0x1
TIMER1 = 0xfe85fae9, TIMER2 = 0x1
TIMER1 = 0xff0f7c11, TIMER2 = 0x1
TIMER1 = 0xff98fd39, TIMER2 = 0x1
TIMER1 = 0xf0227e61, TIMER2 = 0x1  --------------------> 8th OverFlow
TIMER1 = 0xf0abff89, TIMER2 = 0x1
TIMER1 = 0xf13580ab, TIMER2 = 0x1
TIMER1 = 0xf1bf01df, TIMER2 = 0x1
TIMER1 = 0xf2488301, TIMER2 = 0x1
TIMER1 = 0xf2d20429, TIMER2 = 0x1
TIMER1 = 0xf35b854b, TIMER2 = 0x1
TIMER1 = 0xf3e5067f, TIMER2 = 0x1
TIMER1 = 0xf46e87a7, TIMER2 = 0x1
TIMER1 = 0xf4f808c9, TIMER2 = 0x1
TIMER1 = 0xf58189f1, TIMER2 = 0x1
TIMER1 = 0xf60b0b0d, TIMER2 = 0x1
TIMER1 = 0xf6948c35, TIMER2 = 0x1
TIMER1 = 0xf71e0d5d, TIMER2 = 0x1
TIMER1 = 0xf7a78e85, TIMER2 = 0x1
TIMER1 = 0xf8310fa7, TIMER2 = 0x1
TIMER1 = 0xf8ba90cf, TIMER2 = 0x1
TIMER1 = 0xf94411f7, TIMER2 = 0x1
TIMER1 = 0xf9cd931f, TIMER2 = 0x1
TIMER1 = 0xfa571447, TIMER2 = 0x1
TIMER1 = 0xfae09569, TIMER2 = 0x1
TIMER1 = 0xfb6a1697, TIMER2 = 0x1
TIMER1 = 0xfbf397c5, TIMER2 = 0x1
TIMER1 = 0xfc7d18e7, TIMER2 = 0x1
TIMER1 = 0xfd069a09, TIMER2 = 0x1
TIMER1 = 0xfd901b2b, TIMER2 = 0x1
TIMER1 = 0xfe199c47, TIMER2 = 0x1
TIMER1 = 0xfea31d75, TIMER2 = 0x1
TIMER1 = 0xff2c9e97, TIMER2 = 0x1
TIMER1 = 0xffb61fbf, TIMER2 = 0x1
TIMER1 = 0xf03fa0ed, TIMER2 = 0x4  --------------------> 9th OverFlow
TIMER1 = 0xf0c92215, TIMER2 = 0x4
TIMER1 = 0xf152a33d, TIMER2 = 0x4
TIMER1 = 0xf1dc2465, TIMER2 = 0x4
TIMER1 = 0xf265a587, TIMER2 = 0x4
TIMER1 = 0xf2ef26bb, TIMER2 = 0x4
TIMER1 = 0xf378a7dd, TIMER2 = 0x4
TIMER1 = 0xf4022905, TIMER2 = 0x4
TIMER1 = 0xf48baa27, TIMER2 = 0x4
TIMER1 = 0xf5152b5b, TIMER2 = 0x4
TIMER1 = 0xf59eac83, TIMER2 = 0x4
TIMER1 = 0xf6282da5, TIMER2 = 0x4
TIMER1 = 0xf6b1aecd, TIMER2 = 0x4
TIMER1 = 0xf73b2fe9, TIMER2 = 0x4
TIMER1 = 0xf7c4b111, TIMER2 = 0x4
TIMER1 = 0xf84e3239, TIMER2 = 0x4
TIMER1 = 0xf8d7b361, TIMER2 = 0x4
TIMER1 = 0xf961348f, TIMER2 = 0x4
TIMER1 = 0xf9eab5b7, TIMER2 = 0x4
TIMER1 = 0xfa7436df, TIMER2 = 0x4
TIMER1 = 0xfafdb801, TIMER2 = 0x4
TIMER1 = 0xfb87392f, TIMER2 = 0x4
TIMER1 = 0xfc10ba57, TIMER2 = 0x4
TIMER1 = 0xfc9a3b7f, TIMER2 = 0x4
TIMER1 = 0xfd23bca7, TIMER2 = 0x4
TIMER1 = 0xfdad3dc9, TIMER2 = 0x4
TIMER1 = 0xfe36bef7, TIMER2 = 0x4
TIMER1 = 0xfec04025, TIMER2 = 0x4
TIMER1 = 0xff49c141, TIMER2 = 0x4
TIMER1 = 0xffd34269, TIMER2 = 0x4
TIMER1 = 0xf05cc38b, TIMER2 = 0x4  --------------------> 10th OverFlow
TIMER1 = 0xf0e644b3, TIMER2 = 0x4
TIMER1 = 0xf16fc5db, TIMER2 = 0x4
TIMER1 = 0xf1f94703, TIMER2 = 0x4
TIMER1 = 0xf282c82b, TIMER2 = 0x4
TIMER1 = 0xf30c4959, TIMER2 = 0x4
TIMER1 = 0xf395ca7b, TIMER2 = 0x4
TIMER1 = 0xf41f4ba3, TIMER2 = 0x4
TIMER1 = 0xf4a8ccd1, TIMER2 = 0x4
TIMER1 = 0xf5324df9, TIMER2 = 0x4
TIMER1 = 0xf5bbcf21, TIMER2 = 0x4
TIMER1 = 0xf6455049, TIMER2 = 0x4
TIMER1 = 0xf6ced16b, TIMER2 = 0x4
TIMER1 = 0xf7585287, TIMER2 = 0x4
TIMER1 = 0xf7e1d3bb, TIMER2 = 0x4
TIMER1 = 0xf86b54dd, TIMER2 = 0x4
TIMER1 = 0xf8f4d605, TIMER2 = 0x4
TIMER1 = 0xf97e572d, TIMER2 = 0x4
TIMER1 = 0xfa07d849, TIMER2 = 0x4
TIMER1 = 0xfa915971, TIMER2 = 0x4
TIMER1 = 0xfb1ada99, TIMER2 = 0x4
TIMER1 = 0xfba45bc1, TIMER2 = 0x4
TIMER1 = 0xfc2ddcef, TIMER2 = 0x4
TIMER1 = 0xfcb75e17, TIMER2 = 0x4
TIMER1 = 0xfd40df3f, TIMER2 = 0x4
TIMER1 = 0xfdca6061, TIMER2 = 0x4
TIMER1 = 0xfe53e18f, TIMER2 = 0x4
TIMER1 = 0xfedd62b7, TIMER2 = 0x4
TIMER1 = 0xff66e3df, TIMER2 = 0x4
TIMER1 = 0xfff06507, TIMER2 = 0x4
TIMER1 = 0xf079e629, TIMER2 = 0x4  --------------------> 11th OverFlow
TIMER1 = 0xf1036757, TIMER2 = 0x4
TIMER1 = 0xf18ce885, TIMER2 = 0x4
TIMER1 = 0xf21669a1, TIMER2 = 0x4
TIMER1 = 0xf29feac9, TIMER2 = 0x4
TIMER1 = 0xf3296beb, TIMER2 = 0x4
TIMER1 = 0xf3b2ed07, TIMER2 = 0x4
TIMER1 = 0xf43c6e35, TIMER2 = 0x4
TIMER1 = 0xf4c5ef57, TIMER2 = 0x4
TIMER1 = 0xf54f707f, TIMER2 = 0x4
TIMER1 = 0xf5d8f1ad, TIMER2 = 0x4
TIMER1 = 0xf66272d5, TIMER2 = 0x4
TIMER1 = 0xf6ebf3fd, TIMER2 = 0x4
TIMER1 = 0xf7757525, TIMER2 = 0x4
TIMER1 = 0xf7fef647, TIMER2 = 0x4
TIMER1 = 0xf8887775, TIMER2 = 0x4
TIMER1 = 0xf911f89d, TIMER2 = 0x4
TIMER1 = 0xf99b79cb, TIMER2 = 0x4
TIMER1 = 0xfa24fae7, TIMER2 = 0x4
TIMER1 = 0xfaae7c1b, TIMER2 = 0x4
TIMER1 = 0xfb37fd3d, TIMER2 = 0x4
TIMER1 = 0xfbc17e65, TIMER2 = 0x4
TIMER1 = 0xfc4aff8d, TIMER2 = 0x4
TIMER1 = 0xfcd480b5, TIMER2 = 0x4
TIMER1 = 0xfd5e01dd, TIMER2 = 0x4
TIMER1 = 0xfde782ff, TIMER2 = 0x4
TIMER1 = 0xfe71042d, TIMER2 = 0x4
TIMER1 = 0xfefa8555, TIMER2 = 0x4
TIMER1 = 0xff84067d, TIMER2 = 0x4
TIMER1 = 0xf00d87a5, TIMER2 = 0x7  --------------------> 12th OverFlow
TIMER1 = 0xf09708c7, TIMER2 = 0x7
TIMER1 = 0xf12089e3, TIMER2 = 0x7
TIMER1 = 0xf1aa0b05, TIMER2 = 0x7
TIMER1 = 0xf2338c33, TIMER2 = 0x7
TIMER1 = 0xf2bd0d61, TIMER2 = 0x7
TIMER1 = 0xf3468e7d, TIMER2 = 0x7
TIMER1 = 0xf3d00fa5, TIMER2 = 0x7
TIMER1 = 0xf45990c7, TIMER2 = 0x7
TIMER1 = 0xf4e311ef, TIMER2 = 0x7
TIMER1 = 0xf56c9317, TIMER2 = 0x7
TIMER1 = 0xf5f6143f, TIMER2 = 0x7
TIMER1 = 0xf67f9567, TIMER2 = 0x7
TIMER1 = 0xf7091695, TIMER2 = 0x7
TIMER1 = 0xf79297b7, TIMER2 = 0x7

From the above logs:

1) It seems to take around 6 overflows in TIMER 1 to get the 1st increment in TIMER2

2) After the 1st increment, the TIMER2 gets incremented 3 timers after every 3rd overflow of TIMER 1

Whereas, the expectation is:

TINMER2 should increment at every overflow of TIMER 1

How do we implement the cascaded timer feature? Is there anything wrong with the above implementation?

  • +1
    TI__Mastermind 42125 points

    Hi,

    There is a timer register synchronization delay between the Bus clock domain and the Timer Counter domain.  Reading/Writing to any of the following registers:

    TCLR, TLDR, TCRR, TTGR, TMAR, TPIR, TNIR, TCVR, TOCR and TOWR

    Requires synchronization to the Timer clock domain before completion.  This delay is

    1 CBA Clock + 3 Timer Clocks.

    which explains the behaviors. Since the pulse from the overflow event of TIMER1 works as the Timer clock for TIMER2, you see it increment by three every three overflows. 
    The timer will increment properly, but polling will have the synchronization delay. It works better to use the timer to generate interrupts to the CPU based on the compare or overflow events.

    Please try the following sample code:

    Cascaded_Timer_csl.zip

    To try this at your end, download the zip file attached above, extract and replace dmTimer_funcTest.c at <PDK>/packages/ti/csl/test/dmTimerUt

    and build the dmTimer test.

    Please see the logs attached

     DmTimer Test Application
Interrupt_reg passed
Interrupt_reg 2 passed
Cascaded Timer Test
Overflow in TIMER1 increments TCRR in TIMER2
EXP 1: Enabling TIMER1 after enabling TIMER2
Enabling Cascade

MMR is unlocked in BoardInit

Setting up timer 1
[TIMER1]: Write to TLDR
[TIMER1]: Write Pending - TLDR
[TIMER1]: Write to TTGR
[TIMER1]: Write Pending TTGR
[TIMER1]: Write to IRQ
[TIMER1]: Write to TCLR
[TIMER1]: Write Pending - TCLR
Setting up timer 2
[TIMER2]: Write to TLDR
[TIMER2]: Write Pending - TLDR
[TIMER2]: Write to TTGR
[TIMER2]: Write Pending TTGR
[TIMER2]: Write to IRQ                                                               
[TIMER2]: Write to TCLR                                                              
[TIMER2]: Write Pending - TCLR                                                       
Before Setting up timer2 OVF-1 0 OVF-2 0                                             
Before Starting timer2 OVF-1 10 OVF-2 0                                              
Just after starting timer2 OVF-1 11 OVF-2 0
Both timer are up and running
OVF-1 12 OVF-2 0
OVF-1 13 OVF-2 0
OVF-1 14 OVF-2 0
OVF-1 15 OVF-2 0
OVF-1 16 OVF-2 0
OVF-1 17 OVF-2 1
OVF-1 18 OVF-2 1
OVF-1 19 OVF-2 1
OVF-1 20 OVF-2 1
OVF-1 21 OVF-2 1
OVF-1 22 OVF-2 1
OVF-1 23 OVF-2 2
OVF-1 24 OVF-2 2
OVF-1 25 OVF-2 2
OVF-1 26 OVF-2 2
OVF-1 27 OVF-2 2
OVF-1 28 OVF-2 2
OVF-1 29 OVF-2 3
OVF-1 30 OVF-2 3
OVF-1 31 OVF-2 3
OVF-1 32 OVF-2 3
OVF-1 33 OVF-2 3
OVF-1 34 OVF-2 3
OVF-1 35 OVF-2 4
OVF-1 36 OVF-2 4
OVF-1 37 OVF-2 4
OVF-1 38 OVF-2 4
OVF-1 39 OVF-2 4
OVF-1 40 OVF-2 4

    From the logs you can see that:

    Here the TLDR value for TIMER2 is 0xFFFF_FFFA which means that it will overflow after every 6 overflows in TIMER1 and the same can be observed from the logs

    In conclusion, the TIMER2 does increment as expected, but polling the TCRR register does not provide the correct value. 

    Regards,
    Parth