SK-AM62: Unable to Access SPI Interface from 40-Pin Expansion Connector on AM62xx EVM Running Debian OS

Hi Kasun,

we don't have a specific "step by step guide" for Debian but this is really a Kernel and Kernel-configuration (Device Tree)-related concern so anything we have on "Linux SPI" really applies here. Debian-specific differences would be how to deploy/integrate updated Kernel / Device Tree Files but that hopefully shouldn't be too difficult to figure out (our Debian SDK documentation would be a good starting point).

Assuming you want to do what's called "Usermode SPI", s for using Linux / SPI see...

1. See the "Linux Userspace Interface" section in the AM62x Linux SDK documentation for a general starting point, and how to enable a required Kernel configuration:
   https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/09_02_01_10/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/SPI.html
2. For how to make the needed Device Tree changes (and common issues related to this), see this E2E post/thread here:
   https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1263441/sk-am62-no-spi-signals-on-expansion-headers/4783737

Regards, Andreas

Hi Andreas,

Thank you for your response.

I'll try and make an update on this.

Regards,
Kasun

Hi Andreas, 

I am currently working with an AM62xx Evaluation Module (EVM) and using the 09.02.01.10 SDK (dated 22 May 2024) along with the tisdk-debian-bookworm-am62xx-evm.wic.xz operating system. 

In the kernel configuration file, CONFIG_SPI_SPIDEV=m is set as default. Additionally, config.gz does not allow modifications. The following are the relevant Device Tree Blob Overlay (DTBO) files located in the /boot/dtb/ti directory. The device tree file for my processor board is k3-am625-sk.dtb. 

root@am62xx-evm:/boot/dtb/ti# ls  

k3-am62-lp-sk-lincolntech-lcd185-panel.dtbo
k3-am62-lp-sk-microtips-mf101hie-panel.dtbo
k3-am62-lp-sk-nand.dtbo
k3-am62-lp-sk.dtb
k3-am625-beagleplay-csi2-ov5640.dtbo
k3-am625-beagleplay-csi2-tevi-ov5640.dtbo
k3-am625-beagleplay-lincolntech-lcd185-panel.dtbo
k3-am625-beagleplay.dtb
k3-am625-sk-dmtimer-pwm.dtbo
k3-am625-sk-ecap-capture.dtbo
k3-am625-sk-lincolntech-lcd185-panel.dtbo
k3-am625-sk-mcspi-loopback.dtbo
k3-am625-sk-microtips-mf101hie-panel.dtbo
k3-am625-sk-microtips-mf103hie-lcd2.dtbo
k3-am625-sk-pwm.dtbo
k3-am625-sk-rpi-hdr-ehrpwm.dtbo
k3-am625-sk.dtb
k3-am62a7-sk-csi2-imx219.dtb
k3-am62a7-sk-csi2-ox05b1s.dtbo
k3-am62a7-sk-e3-max-opp.dtbo
k3-am62a7-sk-ethernet-dc01.dtbo
k3-am62a7-sk-fusion-imx390.dtb
k3-am62a7-sk-fusion-ov2312.dtb
k3-am62a7-sk-rpi-hdr-ehrpwm.dtbo
k3-am62a7-sk-ub954-evm-ov2312.dtb
k3-am62p5-sk-dsi-rpi-7inch-panel.dtbo
k3-am62p5-sk-dss-shared-mode.dtbo
k3-am62p5-sk-eqep.dtbo
k3-am62p5-sk-mcan.dtbo
k3-am62p5-sk-microtips-mf101hie-panel.dtbo
k3-am62p5-sk-microtips-mf103hie-lcd2.dtbo
k3-am62p5-sk-rpi-hdr-ehrpwm.dtbo
k3-am62p5-sk.dtb
k3-am62x-sk-csi2-imx219.dtbo
k3-am62x-sk-csi2-ov5640.dtbo
k3-am62x-sk-csi2-tevi-ov5640.dtbo
k3-am62x-sk-csi2-v3link-fusion.dtbo
k3-am62x-sk-eqep.dtbo
k3-am62x-sk-hdmi-audio.dtbo
k3-am62x-sk-hdmi-disable-fastboot.dtbo
k3-am62x-sk-lpm-wkup-sources.dtbo
k3-am62x-sk-mcan.dtbo
k3-am642-evm-icssg1-dualemac-mii.dtbo
k3-am642-evm-icssg1-dualemac.dtbo
k3-am642-evm-nand.dtbo
k3-am642-evm.dtb
k3-am642-sk.dtb
k3-am6528-iot2050-basic-pg2.dtb
k3-am6528-iot2050-basic.dtb
k3-am654-base-board.dtb
k3-am654-evm-oldi-lcd1evm.dtbo
k3-am654-idk.dtbo
k3-am654-pcie-usb2.dtbo
k3-am654-pcie-usb3.dtbo
k3-am6548-iot2050-advanced-pg2.dtb
k3-am6548-iot2050-advanced.dtb
k3-am68-sk-base-board.dtb
k3-am68-sk-bb-csi2-ov5640.dtbo
k3-am68-sk-bb-rpi-cam-imx219.dtbo
k3-am68-sk-fpdlink-fusion.dtbo
k3-am68-sk-rpi-hdr-ehrpwm.dtbo
k3-am68-sk-som-ddr-mem-carveout.dtbo
k3-am68-sk-v3link-fusion.dtbo
k3-am69-sk-csi2-ov5640.dtbo
k3-am69-sk-csi2-rpi-cam-imx219.dtbo
k3-am69-sk-csi2-v3link-fusion.dtbo
k3-am69-sk-ddr-mem-carveout.dtbo
k3-am69-sk-fpdlink-fusion-auxport.dtbo
k3-am69-sk-fpdlink-fusion.dtbo
k3-am69-sk-rpi-hdr-ehrpwm.dtbo
k3-am69-sk.dtb
k3-fpdlink-imx390-rcm-0-0.dtbo
k3-fpdlink-imx390-rcm-0-1.dtbo
k3-fpdlink-imx390-rcm-0-2.dtbo
k3-fpdlink-imx390-rcm-0-3.dtbo
k3-fpdlink-imx390-rcm-1-0.dtbo
k3-fpdlink-imx390-rcm-1-1.dtbo
k3-fpdlink-imx390-rcm-1-2.dtbo
k3-fpdlink-imx390-rcm-1-3.dtbo
k3-fpdlink-imx390-rcm-2-0.dtbo
k3-fpdlink-imx390-rcm-2-1.dtbo
k3-fpdlink-imx390-rcm-2-2.dtbo
k3-fpdlink-imx390-rcm-2-3.dtbo
k3-fpdlink-ov2312-0-0.dtbo
k3-fpdlink-ov2312-0-1.dtbo
k3-fpdlink-ov2312-0-2.dtbo
k3-fpdlink-ov2312-0-3.dtbo
k3-j7200-evm-mcspi-loopback.dtbo
k3-j7200-evm-virt-mac-client.dtbo
k3-j7200-evm.dtb
k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtbo
k3-j721e-beagleboneai64.dtb
k3-j721e-common-proc-board-infotainment.dtbo
k3-j721e-evm-csi2-ov5640.dtbo
k3-j721e-evm-fusion.dtbo
k3-j721e-evm-gesi-exp-board.dtbo
k3-j721e-evm-pcie0-ep.dtbo
k3-j721e-evm-virt-mac-client.dtbo
k3-j721e-evm.dtb
k3-j721e-sk-csi2-ov5640.dtbo
k3-j721e-sk-csi2-rpi-imx219.dtbo
k3-j721e-sk-fusion.dtbo
k3-j721e-sk-rpi-hdr-ehrpwm.dtbo
k3-j721e-sk.dtb
k3-j721s2-common-proc-board.dtb
k3-j721s2-evm-csi2-ov5640.dtbo
k3-j721s2-evm-fusion.dtbo
k3-j721s2-evm-gesi-exp-board.dtbo
k3-j721s2-evm-pcie1-ep.dtbo
k3-j722s-evm-csi2-ov5640.dtbo
k3-j722s-evm-csi2-rpi-cam-imx219.dtbo
k3-j722s-evm-csi2-tevi-ov5640.dtbo
k3-j722s-evm-dsi-rpi-7inch-panel.dtbo
k3-j722s-evm-fpdlink-fusion.dtbo
k3-j722s-evm-microtips-mf101hie-panel.dtbo
k3-j722s-evm-v3link-fusion.dtbo
k3-j722s-evm.dtb
k3-j784s4-evm-csi2-ov5640.dtbo
k3-j784s4-evm-quad-port-eth-exp1.dtbo
k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
k3-j784s4-evm-virt-mac-client.dtbo
k3-j784s4-evm.dtb
k3-v3link-imx219-0-0.dtbo
k3-v3link-imx219-0-1.dtbo
k3-v3link-imx219-0-2.dtbo
k3-v3link-imx219-0-3.dtbo

 I have decompiled the k3-am625-sk.dtb using the device-tree-compiler installed via apt (the decompiled file is attached). 

On the E2E forum(https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1263441/sk-am62-no-spi-signals-on-expansion-headers/4783737), it was suggested to add the following configuration to the Device Tree Blob (DTB) and compile it: 

.............................................................................................................................. 

main_spi0_pins_default: main-spi0-pins-default {  
   pinctrl-single,pins = <  
       AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK */  
       AM62X_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B13) SPI0_D0 */  
       AM62X_IOPAD(0x01c4, PIN_INPUT, 0) /* (B14) SPI0_D1 */  
       AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 */  
   >;  
};  
 
&spi1 {  
   status = "okay";  
   pinctrl-names = "default";  
   pinctrl-0 = <&spi1_pins_s0>;  
   spidev@1 {  
       spi-max-frequency = <24000000>;  
       reg = <0>;  
       compatible = "rohm,dh2228fv";  
   };  
}; 
 

..................................................................................................................

However, I am unsure where exactly to place above configuration within the DTB. Additionally, I would appreciate some clarification on the purpose of the k3-am625-sk-mcspi-loopback.dtbo file. 

Could you please provide guidance on resolving this issue? I am new to working with this processor board and Linux kernel configurations.Please provide step-by-step guidance.

Thank you for your assistance. 

Best regards, 

Kasun 

7357.DTS.txt

kasun kavindu said:

In the kernel configuration file, CONFIG_SPI_SPIDEV=m is set as defau

If it is set to be build as a module it should work, the driver ("module") will get loaded as the device tree is being parsed and processed.

kasun kavindu said:

However, I am unsure where exactly to place above configuration within the DTB.

You can just add this section to the k3-am625-sk.dts original source file directly, and then compile this source file. This is best done in the context of the Linux kernel source used for the Debian SDK. The Debian SDK User's Guide has steps that show how to re-build the kernel package so you can just follow this in order to build a kernel package that has the device tree you updated: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/09_02_01_Debian/exports/docs/debian/Building_Debian_Packages.html

kasun kavindu said:

Additionally, I would appreciate some clarification on the purpose of the k3-am625-sk-mcspi-loopback.dtbo file. 

You can use U-Boot to apply this overlay file on top of another device tree blob (such as k3-am625-sk.dtb), effectively merging the two in binary context. To do that stop U-Boot so you get the prompt, and enter...

=> env set name_overlays k3-am625-sk.dtb

...and then start the boot process using...

=> boot

This should establish a basic working SPI configuration you can exercise using userspace applications (such as spidev_test.c, that comes with the kernel).

Regards, Andreas

Hi Andreas,

Thank you for the valuable response. It was very helpful.

I successfully enabled the SPIDEV interface and tested the SPI0 channel using the spidev_test.c with a loopback configuration. The spidev1.0 device appears in the /dev/ directory. Below are the steps I followed:

Upon connecting spi0_D1 and spi0_D0 together, I obtained the following results:

I guess,this confirms that the SPI0 channel is configured and working properly. Below is the content of the k3-am625-sk-mcspi-loopback.dts:

............................................................................................................................................................................

Now, I would like to enable the SPI2 channel in the EXPANSION HEADER of 40 pin. I need to enable both spi0 and spi2. Is there a straightforward and proper method to do this? I am also unsure how the hex values (e.g., pinctrl-single,pins = <0x1bc 0x50000 0x1c0 0x50000 0x1c4 0x50000 0x1b4 0x50000>;) were derived in the above shown k3-am625-sk-mcspi-loopback.dts.

Can I modify the above k3-am625-sk-mcspi-loopback.dts to enable SPI2 with its pin configurations? If so, what specific changes should be made to the k3-am625-sk-mcspi-loopback.dts?

Any guidance on this matter would be greatly appreciated.

Thank you.

Best regards,

Kasun

kasun kavindu said:

Now, I would like to enable the SPI2 channel in the EXPANSION HEADER of 40 pin. I need to enable both spi0 and spi2. Is there a straightforward and proper method to do this?

You can follow what was done in this post here and edit the DTS source file accordingly: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1249053/am625-testing-spi-interface-on-am625-based-custom-board/4752269#4752269  It shows how to setup both the needed pinmux and additions needed to enable the main_spi2 node.

Regards, Andreas

Hi Andreas,

Thank you very much for the reply.  

SPI0 was successfully enabled using k3-am625-sk-mcspi-loopback.dtbo. “saveenv” is also not working in U-Boot. So it is not permanent. after a normal reboot spidev1.0 is not in /dev/. 

 In this (https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1263441/sk-am62-no-spi-signals-on-expansion-headers/4783737) thread, It is mentioned that they have build the device tree using k3-am62x-sk-common.dtsi.But /boot/dtb/ti/k3-am62x-sk-common.dtb not exits in our Debian OS. 
 

Is it required to build the kernel again by using SDK? But we tried to build the kernel using “make linux”, but errors came. Provide some guidance. Other thing is it enough to change the k3-am62x-sk-common.dtsi and build the kernel to enable spi? 

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Our goal is to enable both spi0 and spi2 in expansion header of 40 pin. 

We changed k3-am625-sk-mcspi-loopback.dtbo for spi2 same as spi0 as shown below. 

/dts-v1/; 
 
/ { 
 
fragment@0 { 
target = <0xffffffff>; 
 
__overlay__ { 
 
main-spi0-pins-default { 
pinctrl-single,pins = <0x1b0 0x50000 0x198 0x50000 0x194 0x50000 0x1ac 0x50000>; 
phandle = <0x01>; 
}; 
}; 
}; 
 
fragment@1 { 
target = <0xffffffff>; 
 
__overlay__ { 
 
gpio@22 { 
 
en_rpi_3v3 { 
gpio-hog; 
gpios = <0x05 0x00>; 
output-high; 
line-name = "EXP_PS_3V3_EN"; 
}; 
}; 
}; 
}; 
 
fragment@2 { 
target = <0xffffffff>; 
 
__overlay__ { 
status = "okay"; 
#address-cells = <0x01>; 
#size-cells = <0x00>; 
pinctrl-0 = <0x01>; 
pinctrl-names = "default"; 
 
spidev@2 { 
compatible = "rohm,dh2228fv"; 
spi-max-frequency = <0x16e3600>; 
reg = <0x00>; 
}; 
}; 
}; 
 
__fixups__ { 
main_pmx0 = "/fragment@0:target:0"; 
main_i2c1 = "/fragment@1:target:0"; 
main_spi2 = "/fragment@2:target:0"; 
}; 
 
__local_fixups__ { 
 
fragment@2 { 
 
__overlay__ { 
pinctrl-0 = <0x00>; 
}; 
}; 
}; 
} 

After compiling the overlay k3-am625-sk-mcspi-loopback.dtbo was added from the U-boot (same did for spi0) spidev1.0 was /dev/.  

Why spidev1.2 is not created? 

We observed from logic analyzer. But nothing happen for spi2_clk, spi2_CS0, spi2_cs2, spi2_d0, and spi2_d1. 

As in link(https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1350774/sk-am62-main-domain-spi-channel-two/5176728#5176728 ), we tried from CCS, It was successful for below configurations. 

FETBUF_EN =1 

FET_SEL =0 

Could you please provide the necessary guidance to achieve our goal of enabling spi0 and spi2 from tisdk-debian-bookworm-am62xx-evm.wic.xz operating system in same time. 

Best Regards, 

Kasun 

Can you share your .dts* source file please?

Regards, Andreas

5481.DTS.txt

Hi Kasun,

no I was asking for the actual source files, not the de-compiled source files. Usually this is a combination of things taken from the Kernel tree (from arch/arm64/boot/dts/ti/), plus your modifications

Regards, Andreas

Hi Andreas,

// SPDX-License-Identifier: GPL-2.0
/*
 * AM625 SK: https://www.ti.com/lit/zip/sprr448
 *
 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-am62x-sk-common.dtsi"

/ {
	compatible = "ti,am625-sk", "ti,am625";
	model = "Texas Instruments AM625 SK";

	opp-table {
		/* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
		opp-1400000000 {
			opp-hz = /bits/ 64 <1400000000>;
			opp-supported-hw = <0x01 0x0004>;
			clock-latency-ns = <6000000>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* 2G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;

	};

	vmain_pd: regulator-0 {
		/* TPS65988 PD CONTROLLER OUTPUT */
		compatible = "regulator-fixed";
		regulator-name = "vmain_pd";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_5v0: regulator-1 {
		/* Output of LM34936 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vmain_pd>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_3v3_sys: regulator-2 {
		/* output of LM61460-Q1 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_sys";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vmain_pd>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: regulator-3 {
		/* TPS22918DBVR */
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vcc_3v3_sys>;
		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
	};

	vdd_sd_dv: regulator-4 {
		/* Output of TLV71033 */
		compatible = "regulator-gpio";
		regulator-name = "tlv71033";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vcc_5v0>;
		gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};

	vcc_1v8: regulator-5 {
		/* output of TPS6282518DMQ */
		compatible = "regulator-fixed";
		regulator-name = "vcc_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vcc_3v3_sys>;
		regulator-always-on;
		regulator-boot-on;
	};

	wlan_lten: regulator-6 {
		compatible = "regulator-fixed";
		regulator-name = "wlan_lten";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc_3v3_sys>;
		gpios = <&exp1 11 GPIO_ACTIVE_LOW>;
	};

	wlan_en: regulator-7 {
		compatible = "regulator-fixed";
		regulator-name = "wlan_en";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&wlan_lten>;
		enable-active-high;
		gpios = <&main_gpio0 71 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&wlan_en_pins_default>;
	};

	vdd_core: regulator-8 {
		/* output of TPS62826DMQ */
		compatible = "regulator-fixed";
		regulator-name = "vdd_core";
		regulator-min-microvolt = <850000>;
		regulator-max-microvolt = <850000>;
		vin-supply = <&vcc_3v3_sys>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&main_pmx0 {
	main_rgmii2_pins_default: main-rgmii2-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
			AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
			AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
			AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
			AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
			AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
		>;
	};

	ospi0_pins_default: ospi0-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
			AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
			AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
			AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
			AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
			AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
			AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
			AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
			AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
			AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
			AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
		>;
	};

	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
		>;
	};

	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
		>;
	};

	wlan_en_pins_default: wlan-en-pins-default {
		pinctrl-single,pins = <
				AM62X_IOPAD(0x124, PIN_OUTPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */
		>;
	};

	main_mmc2_pins_default: main-mmc2-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */
			AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */
			AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */
			AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */
			AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */
			AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */
			AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */
		>;
	};

	main_wlirq_pins_default: main-wlirq-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */
		>;
	};
};

&main_i2c1 {
	exp1: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
				   "PRU_DETECT", "MMC1_SD_EN",
				   "VPP_LDO_EN", "EXP_PS_3V3_En",
				   "EXP_PS_5V0_En", "EXP_HAT_DETECT",
				   "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
				   "UART1_FET_BUF_EN", "WL_LT_EN",
				   "GPIO_HDMI_RSTn", "CSI_GPIO1",
				   "CSI_GPIO2", "PRU_3V3_EN",
				   "HDMI_INTn", "PD_I2C_IRQ",
				   "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
				   "MCASP1_FET_SEL", "UART1_FET_SEL",
				   "TSINT#", "IO_EXP_TEST_LED";

		interrupt-parent = <&main_gpio1>;
		interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;

		pinctrl-names = "default";
		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
	};
};

&sdhci1 {
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv>;
};

&sdhci2 {
	status = "okay";
	vmmc-supply = <&wlan_en>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc2_pins_default>;
	bus-width = <4>;
	non-removable;
	ti,fails-without-test-cd;
	cap-power-off-card;
	keep-power-in-suspend;
	assigned-clocks = <&k3_clks 157 158>;
	assigned-clock-parents = <&k3_clks 157 160>;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@2 {
		compatible = "ti,wl1837";
		reg = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_wlirq_pins_default>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <72 IRQ_TYPE_EDGE_RISING>;
	};
};

&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&main_rgmii1_pins_default
		     &main_rgmii2_pins_default>;

	cpts@3d000 {
		/* MAP HW3_TS_PUSH to GENF1 */
		ti,pps = <2 1>;
	};
};

&cpsw_port2 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy1>;
};

&cpsw3g_mdio {
	cpsw3g_phy1: ethernet-phy@1 {
		reg = <1>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&ospi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "ospi.tiboot3";
				reg = <0x0 0x80000>;
			};

			partition@80000 {
				label = "ospi.tispl";
				reg = <0x80000 0x200000>;
			};

			partition@280000 {
				label = "ospi.u-boot";
				reg = <0x280000 0x400000>;
			};

			partition@680000 {
				label = "ospi.env";
				reg = <0x680000 0x40000>;
			};

			partition@6c0000 {
				label = "ospi.env.backup";
				reg = <0x6c0000 0x40000>;
			};

			partition@800000 {
				label = "ospi.rootfs";
				reg = <0x800000 0x37c0000>;
			};

			partition@3fc0000 {
				label = "ospi.phypattern";
				reg = <0x3fc0000 0x40000>;
			};
		};
	};
};

&tlv320aic3106 {
	DVDD-supply = <&vcc_1v8>;
};

#define K3_TS_OFFSET(pa, val)	(0x4+(pa)*4) (0x10000 | val)

&timesync_router {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&cpsw_cpts>;

	/* Use Time Sync Router to map GENF1 input to HW3_TS_PUSH output */
	cpsw_cpts: cpsw-cpts {
		pinctrl-single,pins = <
			/* pps [cpsw cpts genf1] in17 -> out12 [cpsw cpts hw3_push] */
			K3_TS_OFFSET(12, 17)
			>;
	};
};

Regards,

Kasun