DRA821U: LPDDR Speed issue

Hi,

Kaushal C said:

Also why is latest SDK having 2666 MT/S instead of 3200MT/S. 

The RTOS SDK PDK bootloader supports both 2666 and 3200, depending on the silicon revision of DRA821. 

However, there was unfortunately push back to support two options inside of the Linux SDK (u-boot) at the time these changes were being made - so we had to choose one option. Because some internal software teams were still using older silicon at that time, the decision was made to keep the slower frequency as the default in the SDK to not "break" older boards. However, using the faster frequency is still valid for customers or on newer TI EVMs using the latest silicon. 

Kaushal C said:

When checked in our board, our board boots fine with 2666 MT/S speed but when changed to  board hangs.

How did you change the frequency? What version of the DDR configuration tool was used? Can you provide the filled-in tool settings for both the working and non-working scenarios? 

Can you show a log illustrating the failure? 

Can you comment on the memory being used?

Regards,
Kevin

Hi Kevin,

We are using 2GB LPDDR4 in our board 

Kevin S said:

What version of the DDR configuration tool was used?

Since we couldn't find separate DDR configuration tool for R2.0 we are using the below shown tool 

But inside this tool we could select R2.0 

Kevin S said:

Can you provide the filled-in tool settings for both the working and non-working scenarios?

Attached sysconfig file of working and non working case with just frequency change from 1600 to 1333

3857.Sysconfig.zip

Kevin S said:

Can you show a log illustrating the failure? 

Attached Log of 3 different case where it was hanging

Scenario 1
----------------


U-Boot SPL 2023.04-dirty (Jul 03 2024 - 10:35:40 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
EEPROM not available at 0x54, trying to read at 0x55
Reading on-board EEPROM at 0x55 failed -121
i2c_write: error waiting for data ACK (status=0x116)
read error from device: 41c86594 register: x!
                                                                                 
-----------spl_board_init----------                                              
Trying to boot from MMC2                                                         
Loading Environment from nowhere... OK                                               
Starting ATF on ARM64 core...                                                        
                                                                                     
NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty                        
NOTICE:  BL31: Built : 16:09:05, Feb  9 2024
I/TC: 
I/TC: OP-TEE version: 4.1.0-51-g012cdca49 (gcc version 11.4.0 (GCC)) #1 Tue Jan 30 10:48:03 UTC 2024 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2023.04-dirty (Jul 03 2024 - 10:35:35 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')



Scenario 2
----------------





U-Boot SPL 2023.04-dirty (Jul 03 2024 - 10:35:40 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
EEPROM not available at 0x54, trying to read at 0x55
Reading on-board EEPROM at 0x55 failed -121
i2c_write: error waiting for data ACK (status=0x116)
read error from device: 41c86594 register: x!

-----------spl_board_init----------
Trying to boot from MMC2
Loading Environment from nowhere... OK
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
NOTICE:  BL31: Built : 16:09:05, Feb  9 2024
I/TC: 
I/TC: OP-TEE version: 4.1.0-51-g012cdca49 (gcc version 11.4.0 (GCC)) #1 Tue Jan 30 10:48:03 UTC 2024 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
I/TC: HUK Initialized
E/TC:0 0 k3_sec_proxy_verify_thread:108 Queue is busy
E/TC:0 0 k3_sec_proxy_recv:196 Thread SEC_PROXY_RESPONSE_THREAD verification failed. ret = -65523
E/TC:0 0 ti_sci_get_response:101 Message receive failed (-65523)
E/TC:0 0 ti_sci_do_xfer:150 Failed to get response (-65523)
E/TC:0 0 sa2ul_init:61 Failed to get SA2UL device
E/TC:0 0 call_initcalls:43 Initcall __text_start + 0x000710b8 failed
E/TC:0 0 
E/TC:0 0 Core data-abort at address 0x14 (translation fault)
E/TC:0 0  esr 0x96000005  ttbr0 0x9e8a2000   ttbr1 0x00000000   cidr 0x0
E/TC:0 0  cpu #0          cpsr 0x600003c4
E/TC:0 0  x0  000000009e875000 x1  0000000000000000
E/TC:0 0  x2  0000000000000000 x3  0000000000000000
E/TC:0 0  x4  0000000000000420 x5  000000009e892d70
E/TC:0 0  x6  ffffffffffffffb0 x7  0000000000010cb0
E/TC:0 0  x8  000000009e892f80 x9  000000009e882070
E/TC:0 0  x10 0000000000000000 x11 0000000000000008
E/TC:0 0  x12 0000000000000000 x13 000000009e8aa050
E/TC:0 0  x14 0000000000000000 x15 0000000000000000
E/TC:0 0  x16 000000009e81cb8c x17 0000000000000000
E/TC:0 0  x18 0000000000000000 x19 000000009e8aa3d0
E/TC:0 0  x20 000000009e8aa3d8 x21 000000009e875000
E/TC:0 0  x22 000000009e875000 x23 000000009e875ee0
E/TC:0 0  x24 000000009e874db0 x25 0000000000000000
E/TC:0 0  x26 0000000000000000 x27 0000000000000000
E/TC:0 0  x28 0000000000000000 x29 000000009e8aa360
E/TC:0 0  x30 000000009e81747c elr 000000009e81748c
E/TC:0 0  sp_el0 000000009e8aa360
E/TC:0 0 TEE load address @ 0x9e800000
E/TC:0 0 Call stack:
E/TC:0 0  0x9e81748c
E/TC:0 0  0x9e807d60
E/TC:0 0  0x9e822658
E/TC:0 0  0x9e807f50
E/TC:0 0 Panic 'unhandled pageable abort' at core/arch/arm/kernel/abort.c:582 <abort_handler>
E/TC:0 0 TEE load address @ 0x9e800000
E/TC:0 0 Call stack:
E/TC:0 0  0x9e808168
E/TC:0 0  0x9e81f098
E/TC:0 0  0x9e807920
E/TC:0 0  0x9e804a98






Scenario 3
----------------



U-Boot SPL 2023.04-dirty (Jul 03 2024 - 10:35:40 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
EEPROM not available at 0x54, trying to read at 0x55
Reading on-board EEPROM at 0x55 failed -121
i2c_write: error waiting for data ACK (status=0x116)
read error from device: 41c86594 register: x!

-----------spl_board_init----------
Trying to boot from MMC2
Loading Environment from nowhere... OK
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
NOTICE:  BL31: Built : 16:09:05, Feb  9 2024
I/TC: 
I/TC: OP-TEE version: 4.1.0-51-g012cdca49 (gcc version 11.4.0 (GCC)) #1 Tue Jan 30 10:48:03 UTC 2024 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2023.04-dirty (Jul 03 2024 - 10:35:35 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
EEPROM not available at 0x54, trying to read at 0x55
Reading on-board EEPROM at 0x55 failed -121

-----------spl_board_init----------

--probe daughtercard-----------
Trying to boot from MMC2
am654_sdhci mmc@4fb0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

Kevin S said:

Can you comment on the memory being used?

Since it was hanging in u-boot we couldn't read anything related to memory

Kevin S said:

However, there was unfortunately push back to support two options inside of the Linux SDK (u-boot) at the time these changes were being made - so we had to choose one option. Because some internal software teams were still using older silicon at that time, the decision was made to keep the slower frequency as the default in the SDK to not "break" older boards. However, using the faster frequency is still valid for customers or on newer TI EVMs using the latest silicon. 

Also please suggest if any changes required for 1600 speed, if needed please send you the patch or let us know the changes required

Regards,
Kaushal

Hi Team,

Any updates on use of 1600 speed LPDDR? And I'm using TPS65941515 PMIC which doesn't support AVS voltage change right. So with this PMIC is it possible to change speed to 1600

Regards,
Kaushal

Hi,

Kaushal C said:

Attached sysconfig file of working and non working case with just frequency change from 1600 to 1333

3857.Sysconfig.zip

Thanks, please note that when changing frequency you also need to update the latency parameters.

Kaushal C said:

Attached Log of 3 different case where it was hanging

It looks like it hangs after the DDR initialization. I see in the .syscfg files that you changed the number of ranks from 2 to 1. This implies you have less memory on your board compared to the TI EVM. This wouldn't explain why 1333 works, but at one point in time software required an update to indicate how much total memory is available - which would cause issues if software still assumed 2x the amount of physical memory available. (I do not know if this is still the case). What SDK are your edits based on?

Kaushal C said:

Kevin S said:

Can you comment on the memory being used?

Since it was hanging in u-boot we couldn't read anything related to memory

Sorry, the question was meant to ask which memory part number are you using in your custom board design?

Kaushal C said:

Also please suggest if any changes required for 1600 speed, if needed please send you the patch or let us know the changes required

When you launch the DDR register configuration tool, the default settings are already configured to support LP4-3200 for the DRA821 EVM. 

https://dev.ti.com/sysconfig/?product=TDA4x_DRA8x_AM67x-AM69x_DDR_Config&device=J7200_DRA821_SR1.0_alpha

Regards,
Kevin

Hi Kevin,

Kevin S said:

Thanks, please note that when changing frequency you also need to update the latency parameters.

Can you please provide any documents regarding latency parameter settings that need to be followed for proper working.

Kevin S said:

It looks like it hangs after the DDR initialization. I see in the .syscfg files that you changed the number of ranks from 2 to 1. This implies you have less memory on your board compared to the TI EVM. This wouldn't explain why 1333 works, but at one point in time software required an update to indicate how much total memory is available - which would cause issues if software still assumed 2x the amount of physical memory available. (I do not know if this is still the case). What SDK are your edits based on?

We are using SDK: ti-processor-sdk-linux-j7200-evm-09_02_00_04-Linux-x86-Install. We updated memory node for compatible to 2GB in below mentioned uboot dts file:

file name: arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi

memory@80000000 {
device_type = "memory";
/ 2G RAM /
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
bootph-pre-ram;
};

Kevin S said:

Sorry, the question was meant to ask which memory part number are you using in your custom board design?

LPDDR part used in our board is MT53D512M32D2DS-053 AIT:D

Kaushal C said:

Any updates on use of 1600 speed LPDDR? And I'm using TPS65941515 PMIC which doesn't support AVS voltage change right. So with this PMIC is it possible to change speed to 1600

Also please confirm if 1600 speed is possible without AVS voltage switching?

Regards,
Kaushal

Kaushal C said:

Also please confirm if 1600 speed is possible without AVS voltage switching?

Team,

Please confirm this.

Regards,
Kaushal

Hi Kaushal,

All device variants of DRA821x support a maximum LPDDR4 clock frequency of 1600 MHz (LPDDR4-3200) as indicated in table 7-1 of the datasheet (SPRSP57E).

However, the max frequency is also dependent on the OPP (operating performance point) as indicated in table 7-2. There is a note for table 7-2 that states "OPP and VDD_CPU voltage should be selected/set at boot time. DVFS is not supported." 

According to section 7.3, the active voltage for CPU core supply is "device dependent" and "must be read from the VTM_DEVINFO_VDn" register. 

I'll check internally to confirm, but it doesn't seem that using a static 800 mV for VDD_CPU is a supported use case and it is expected that you should be able to modify the VDD_CPU voltage after reading the specified register.

All this being said, the device selected (DRA821xC) only supports a maximum A72 frequency of 750 MHz. Your system may not benefit from increasing the DDR frequency if the internal cores are operating at slower frequencies. 

~~~~~~~~

In summary,

• The device supports a LPDDR4 clock frequency of 1600 MHz, but requires the VDD_CPU voltage to be set to the OPP_NOM value and not the OPP_LOW value
• Not adjusting VDD_CPU based on the VTM_DEVINFO_VDn registers may not be a valid use case.
• System performance improvements may be minimal when increasing the DDR frequency from 1333 MHz to 1600 MHz if the A72 frequency is limited to 750 MHz.

Regards,
Kevin

Hi Kevin,

So if I change my device to other speed grade of A72 processor and set VDD_CPU voltage to OPP_NOM AVS voltage using TPS65941515 PMIC to change this voltage, I will be able to use DDR at 1600MHz speed without any hanging issue right?

Regards,
Kaushal

Hi Kaushal,

I believe all speed grade variants of DRA821 should  support LPDDR4-3200 at OPP_NOM. The point from my prior response was just to indicate that if the A72 is running at 750 MHz, there may not be substantial performance impact of increasing the DDR frequency from 1333 MHz to 1600 MHz. Thus, it may be more beneficial from a system view to use the slower DDR frequency.

At any rate, we can continue to try and better understand what may be failing when configured at LPDDR4-3200.

Regards,
Kevin

Hi Kevin

Kevin S said:

I believe all speed grade variants of DRA821 should  support LPDDR4-3200 at OPP_NOM. The point from my prior response was just to indicate that if the A72 is running at 750 MHz, there may not be substantial performance impact of increasing the DDR frequency from 1333 MHz to 1600 MHz. Thus, it may be more beneficial from a system view to use the slower DDR frequency.

Understood!! Also please help us to debug LPDDR4-3200. About voltage changes required and support using TPS65941515 PMIC

Regards,
Kaushal

Hi Kevin,

Can you please check on this issue. On how to set LPDDR4-3200, what should be the AVS voltage change required by TPS65941515 PMIC.

Regards,
Kaushal