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AM623: LCD_PCLK setting and EMC RE issues for DPI interface of AM62x DSS

Louis_Vertiv
Intellectual 260 points
Part Number: AM623

Tool/software:

Hi, TI：

      The DPI of the AM623 DSS we use is connected to a 10.1-inch 24-Bit RGB LCD. When testing the EMC RE of the current product, it was found that the LCD_PCLK radiation emission of the DPI port of the AM623 DSS is very strong.

      For example: When testing the LCD_PCLK clock is 31.2MHz, it is found that there is a strong spike at the 5x frequency 155MHz, as shown below：

                 

    When we use the spread spectrum of PLL17, the test found that after the spread spectrum is turned on, the 155MHz spike basically disappears in the background noise, as shown below：the current spread spectrum design is to make it effective by changing the register and then soft restarting.

    

    The EMC RE problem of LCD PCLK of AM623 is very difficult to solve. Using near-field scanning, it is found that the emission of the clock signal is very strong. Please ask TI to help solve it. In addition to the spread spectrum, can the strength of the LCD_PCLK signal be reduced?

    In addition, there is another problem. When modifying the LCD_PCLK clock of panel-simple.c, it is found that when LCD_PCLK is set to a certain clock, after the modified kernel is put into the device startup, LCD_PCLK is not the clock you want to set, but 25MHz, as shown below: set .clock to 33.5MHz, compile the kernel and run it in the device. The LCD_PCLK clock tested with an oscilloscope is 25MHz.

    

  • 0
    TI__Mastermind 35685 points

    Hi,

    With regards to your software issue, please file another ticket and I can help you. For the current ticket, we will focus on the emission issue and my colleague will comment further.

    Regards,
    Krunal

  • 0 in reply to Krunal Bhargav34
    TI__Prodigy 310 points

    Hi,

    For your EMI issue with DPI interface, we do recommend using spread spectrum clocking. Your software implementation looks mainly correct. Are you using the default reference clock frequency of 25MHz? If so, when setting PLL17_SS_SPREAD[19:16] MOD_DIV, we recommend using a value of 0x6 in order to have a modulation rate of 32.6kHz (modulation target typically set above 32kHz). Also, make sure modulation rate is not greater than REFCLK/200 in order to avoid PLL bandwidth violations. Modulation rate is calculated as REFCLK / (128 * MOD_DIV). Note that you might also need to enable PLL17_CTRL[1] DSM_EN in order to make use of fractional divide mode for spread spectrum. I recommend you experiment with lowering PLL17_SS_SPREAD[4:0] SPREAD from 3.1% to 1% in order keep the modulation depth of the LCD_PCLK as small as possible. We have seen 1% modulation depth might be enough to  reduce the peak level of the  interfering frequency in order to pass EMI. This will help to not increase the jitter of the overall system too much.

    Best regards,

    Luis Parga

  • 0 in reply to Luis Parga
    Intellectual 260 points

    Hi, Parga:

        First of all, thank you very much for your help, this is very important for our products.

        Following your way, I reset the spread spectrum, as follows:

            

        I have a question. The clock frequency is 31.2MHz. Using the previous spread spectrum method, as shown in the figure above, the clock frequency measured by the oscilloscope after spread spectrum is about 29MHz, some products have a 29MHz 5-fold frequency spike. Using the spread spectrum method you explained, the frequency measured by the oscilloscope after spread spectrum is still 31.2MHz, all devices can see that the 31.2MHz 5-fold frequency spike has dropped by about 13dB. Is our previous spread spectrum method wrong? Using the method you provided, all products are more consistent.

        In addition, I read the register value of PLL17 and know that the input clock of PLL17 is 25MHz, as shown in the figure below. Is the one in the red box the FREF is the reference clock?

      

  • 0 in reply to Louis_Vertiv
    TI__Prodigy 310 points

    Hi,

    I believe the fmod set to 17.8kHz, how you had it set before, was causing some issues with the VCO. For spread spectrum frequency modulation of the fractional PLL, Silicon Creations recommends fmod >= 32kHz. 

    In this context CLKSSCG and FREF are both 25MHz, since REFDIV is equal to 1. CLKSSCG = FREF/REFDIV.

    Best regards,

    Luis Parga