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AM3359: DDR3 Clock/Address signals routing order fly by topology

Part Number: AM3359

Tool/software:

Hello All,

AM3359 Processor SoC is having a DDR3L interface(2 nos of 4Gb x8 DDR3 chips MT41K512M8) in our board. We are planning to run at max speed of 400MHz DDR3 clock and max addressing of 1GB as per the datasheet. Board is in the final layout review stage and fly by termination topology is followed. Clock/Address/Command signals are routed first to 2nd DDR3 SDRAM (DDR chip with DQ8 to DQ15) and then next to 1st DDR3 SDRAM(DQ0 to DQ7) before getting terminated as shown in the block diagram. Is it fine to route the clock/address/command signals in this order ? Please let me know.