TDA4VE-Q1: Whether Application SW can be loaded after lockstep testing is completed during boot phase

Hi,

Some text from the device TRM below

PDF: https://www.ti.com/lit/zip/spruj28 

HTML: https://www.ti.com/document-viewer/lit/html/spruj28 

Lockstep vs single step / split, is a boot time decision, where when in lockstep the 2nd core is used as a redundancy check on the 1st core.

6.3.2.2 R5FSS Cortex-R5F Core

The Cortex-R5F is a processor from Arm, which is based on the Armv7-R profile. Each R5FSS implements two
R5F cores, CPU0 and CPU1, each with their own RAMs and interfaces. While in reset, they can be bootstrapped
to work in one of two modes: split or lockstep.

In split mode, each R5F core works completely independent from the other (asymmetric multi-processing, or
AMP). Each core uses its own RAMs and interfaces, with no coherence between the two cores. The onlyrestriction is that CPU0 must be in a higher power/reset state than CPU1. For instance, CPU1 cannot be out of reset if CPU0 is not.

In lock-step mode, the core logic from CPU1 is used as redundant logic to check for errors in CPU0. Comparison logic automatically checks the redundant logic against the primary logic and flags any errors. The CPU1 interfaces are not used in this mode. In previous generations of R5FSS, the CPU1 TCMs were unused in lock mode. In this generation of R5FSS, for more efficient use of available memories, the CPU1 TCMs are stacked on CPU0 TCMs in lock-step mode and are accessible only by CPU0 and CPU0 TCM interface. The TCM size for CPU0 is essentially doubled in lock mode (128KB).

For more detailed description of this processor, see the Arm Cortex-R5 Technical Reference Manual. A brief list of features supported by the R5F processor in this device is given in Section 6.3.1.1, R5FSS Features.

Regards,

kb