This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VH-Q1: the tidl result would be incorrect if the pipeline depth was set value 2

Part Number: TDA4VH-Q1

Tool/software:

Hi,  Ti Expert

if pipeline depth is set to 1,  the tidl results of each frame are correct.  but the pipeline depth is changed to 2 

tivxSetGraphPipelineDepth(graph_, 2);
the tidl results on frame NO 0, 2, 4, 6.... are correct,  but the results on frame NO 1, 3, 5, 7 ... are totally wrong,   why?

you can also have a look at the picture above,  you can see that the pipeline 0 work normally,   but the pipeline 1 does not spend any time on tidl.   so it seems that the pipeline 1 was not trigggered to run

the same application code can work normally in j721s2 8.5sdk   8.6sdk

Is there some issue in the j784s4 sdk 9.2?

Looking forward to your replay!

Thanks