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SK-AM62A-LP: how to prevent any transactions for DDR SDRAM?

Jeff Kim27
Intellectual 280 points
Part Number: SK-AM62A-LP

Tool/software:

Hello,

I'm working at u-boot environment. ( ti-processor-sdk-linux-am62xx-evm-09.01.00.08/board-support/ti-u-boot-2023 ) 

Can I prevent the commands (Active, Precharge, Write, Read) to DRAM during short term by setting some register bits? I quote a similar register example from another controller's manual as below.

Best Regards,

Jeff

QUOTE from another controller's manual

DDRC Halt
Specifies whether DDRC accepts new data read or write transactions.
When this field is 1, DDRC does not accept any new transactions for DDR SDRAM until the field becomes 0.
This field can be used when bypassing initialization and forcing MRW commands.
0 - Accepts new transactions
1 - Completes any remaining transactions and remains halted until you write 0 to this field

UNQUOTE

  • 0
    TI__Guru 72750 points

    Hi Jeff, the controller does not have the feature, but you should be able to accomplish the same thing by disabling the LPSC (local power sleep controller) #11 associated with the DDR data transactions. 

    There should be a driver in u-boot to accomplish this. I would have to ask our software team how to so this from u-boot

    Regards,

    James

  • 0 in reply to JJD
    TI__Guru 72750 points

    Hi Jeff, sorry i didn't mention this in the last post.  I mention this in the email, but just wanted to state here.  Since u-boot runs from DDR, you wouldn't be able to halt DDR data transactions.

    Regards,

    James

  • 0 in reply to JJD
    Intellectual 280 points

    Hi James, I'm sorry to hear that AM62 can't halt it when u-boot runs from DDR. Thank you for the confirmation.

    Best Regards,

    Jeff