Tool/software:
Hello,
I'm working at u-boot environment. ( ti-processor-sdk-linux-am62xx-evm-09.01.00.08/board-support/ti-u-boot-2023 )
Can I prevent the commands (Active, Precharge, Write, Read) to DRAM during short term by setting some register bits? I quote a similar register example from another controller's manual as below.
Best Regards,
Jeff
QUOTE from another controller's manual
DDRC Halt
Specifies whether DDRC accepts new data read or write transactions.
When this field is 1, DDRC does not accept any new transactions for DDR SDRAM until the field becomes 0.
This field can be used when bypassing initialization and forcing MRW commands.
0 - Accepts new transactions
1 - Completes any remaining transactions and remains halted until you write 0 to this field
UNQUOTE