TDA4VH-Q1: Unable to do step through debugging for MCU domain R5 core

I managed to  enter the debugging session . But loading binary fails  when i try to load to MCU1_0 in the main domain.

The loading of firmware is not working even for the other binaries which are not related to vision apps.  I am doing following steps:

1. I am building the binary using the following command

pdk_j784s4_09_02_00_30/packages/ti/build$ make -s ipc_qnx_echo_test_freertos BOARD=j784s4_evm PROFILE=debug

2. Then i run my  ccxl launch file by right clicking on it in the Target configuration tab as shown below

3. It takes me in the debugging view. Below is the state of my cores in debugging window

4. Then i go to the scripting console and run the launch.js file. I get following logs

5. Then i connect to Main_cortex_R5_0_0 core as shown below. The core goes in suspended state.

6. Afterwards i try to  load firmware the firmware ipc_qnx_echo_test_freertos_mcu2_0_debug.xer5f in the MAIN_Cortex_R5_0_0.

7. I get following error message

What could be the issue.

Hi,

Can you test if you are able to load an example without HLOS running? For example, Sciserver or GPIO blink example.
Thanks,

Neehar

I am not running any HLOS. I have removed the uboot from the OSPI partition and hence there is no HLOS boot.  My understanding is that in such a situation the Board will go in no boot mode. One more question. Does the MCU cores used DDR  during code execution or do they use the internal SRAM. After running the launch.js i see that DDR is being configured. I was wondering is it required for the microcontroller code to run ?

Can you point me to the documentation for building these examples?

I built the another binary using  make -s GPIO_LedBLink_TestApp_freertos  PROFILE=DEBUG BOARD=j784s4_evm.  and tried to flash it to MCU1_0 and build one with CORE=mcu2_0 for MCU1_0 in the main domain. BUt i always get the same error as in step 7 above. I also erased the uboot from OSPI so that the board is in noboot mode. Here is how my Main domain UART output looks like

Hi,

Have you set the switches on your board to be in No boot mode?

SW11[1-8] = 1000 1000
SW7[1-8]  = 0111 0000

Thanks,

Neehar

We donot have switches on the board. But i erased uboot from the OSPI. Should't it have the same effect and would make the board enter NO boot on A72 after it doesnot find  bootloader

Hi,

Deepankar maithani said:

Does the MCU cores used DDR  during code execution or do they use the internal SRAM. After running the launch.js i see that DDR is being configured.

The GEL scripts only use SRAM, they initialize DDR but don't need it.

What is your back up boot mode? Using GEL scripts in OSPI boot mode can be tricky since ROM must fail OSPI boot. Please ensure the whole flash is erased to guarantee ROM fails. Additionally, when ROM fails there is a watchdog timer for 180 seconds that will trigger a reset if nothing is loaded, therefore, you must run the GEL script before this happens.

Thanks,

Neehar

We donot have any backup boot mode configured on this hardware

Hi,

Then ensure the whole flash memory is erased and attempt to run the GEL scripts within 180 seconds. Before the watchdog timer triggers reset due to failing to load ROM.
Thanks,

Neehar

Hi,

Following up, is this issue still open?

Thanks,

Neehar

Closing due to inactivity.