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Original question:

TMS320C6657: Two stage boot from SPI NOR flash

TMS320C6678: Question about adding Boot Config Table by Add a section defination at 0x00873500(DDR configuration table addres).

Chuan Xu
Prodigy 50 points
Part Number: TMS320C6678
Other Parts Discussed in Thread: SYSBIOS

Tool/software:

[ CCS Version: 5.5.0.00077 ]

[Custom Board with NO IBL.]

[RTOS, SYS/BIOS]

Hi,

I'm trying to boot a large objet file from SPI-NOR Flash, so it needs to INIT DDR before RBL move the sections into DDR.

C6670 Bootloader: How to append a boot configuration table to a boot table? - Processors forum - Processors - TI E2E support forums

Acording the the post above, I'm also want to Add a Boot Config Table to init DDR in the RBL process. So, I did follows:

1. Add the code below in my app code "main.c":

d

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#pragma DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T emif4Cfg = {
BOOT_EMIF4_ENABLE_pllCtl | \
BOOT_EMIF4_ENABLE_sdRamConfig | \
BOOT_EMIF4_ENABLE_sdRamRefreshCtl | \
BOOT_EMIF4_ENABLE_sdRamTiming1 | \
BOOT_EMIF4_ENABLE_sdRamTiming2 | \
BOOT_EMIF4_ENABLE_sdRamTiming3 | \
BOOT_EMIF4_ENABLE_ddrPhyCtl1 | \
BOOT_EMIF4_ENABLE_sdRamOutImpdedCalCfg,
0, /* pllPrediv */
4, /* pllMult */
0, /* pllPostDiv */
0x63062BB2, /* sdRamConfig */
0, /* sdRamConfig2*/
0x00001453, /* sdRamRefreshCtl */
0x1113783C, /* sdRamTiming1 */
0x30717FE3, /* sdRamTiming2 */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

2. In order build it, I add a memory section defination in my platform, like this:

3. Add the memory mapping in the core.cfg file, like this:

Program.sectMap[".emif4Cfg"]            =   "L2_DDR_CFG";   /* 保存启动参数的配置表的内存段定义 */

Then I rebuild the project, in the output .map file,  I found that  there is no used in L2_DDR_CFG, and also no segment, like this:

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******************************************************************************
TMS320C6x Linker PC v7.4.4
******************************************************************************
>> Linked Wed Aug 28 21:58:55 2024
OUTPUT FILE NAME: <core0.out>
ENTRY POINT SYMBOL: "_c_int00" address: 0c10fbe0
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
L2SRAM_SYS 00800000 00070000 00022226 0004ddda RW X
L2_DDR_CFG 00873500 00000100 00000000 00000100 RW X
L1PSRAM 00e00000 00008000 00000000 00008000 RW X
L1DSRAM 00f00000 00008000 00000000 00008000 RW
MSM_IPC 0c000000 00080000 00080000 00000000 RW X
MSM_SYS0 0c080000 00180000 000b9074 000c6f8c RW X
MSM_APP 0c200000 00200000 00200000 00000000 RW X
DDR3_SYS0 80000000 08000000 00052b00 07fad500 RW X
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Dose this mean RBL will not move anything to the 0x00873500(DDR configuration table address according to the manual file of C6678)? And DDR will NOT be configured in this condition?

Thanks.

  • 0
    Prodigy 50 points

    In the post below, Raja said "TI provided direct boot example does not use the RTSC project. Update the cmd file to run from MSMC and build it."

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/803939/ccs-tms320c6652-spi-boot-failure/2990508?tisearch=e2e-sitesearch&keymatch=emif4cfg#

    But I'm use the RTSC, how to do with it?

  • 0 in reply to Chuan Xu
    TI__Mastermind 25535 points

    Before you start with Direct SPI boot and DDR3 initialization in the direct boot-code,

    make sure, your DDR3 works on the custom board through a simple DDR3 read /write test.

    1. Does your DDR3 test passed while running a gel file through CCS ?

    [FAQ] TMS320C6678: How to load and run the gel file on C6678 EVM? - Processors forum - Processors - TI E2E support forums

    ---

    Have you referred this link for Direct SPI boot ? 

    By any chance you run this on the TI-C6678-EVM for some hands on experience? So that it will be easy to work on the custom board?

    Regards

    Shankari G

  • 0 in reply to Shankari G
    Prodigy 50 points

    Yes, I've run the GEL file to test DDR on my custom board, which works good.

    And I also boot from the SPI-NOR Flash with DDR Config Table on my custom board with the 0647.C6678_directROM_boot_examples.zip\C6678\spiboot\src\led_play\ , GPIO and DDR runs are all good.

    So, I think I can use the same method to boot from SPI directly like I metioned above. 

  • +1 in reply to Chuan Xu
    Prodigy 50 points

    Shankari G

    I just add code  in the main() funtion like this, and it WORKS:

    memset(&emif4Cfg, 0, sizeof(emif4Cfg));

    The Output .map file looks good:

    But in the examples, there is no such problem, it's wired.

  • 0 in reply to Chuan Xu
    TI__Mastermind 25535 points

    Good then.

    You seem to closed the thread.

    You are done or you have any further questions?

    Regards

    Shankari G

  • 0 in reply to Shankari G
    Prodigy 50 points

    Shankari G

    Not yet, here comes a new problem:

    While using the spiboot.bat to create the SPI-NORFlash bootable image, I found After executed   hex6x.exe core0.rmd, in the output core0.mxp file, the .emif4Cfg gone away.

    Here post my output files and  the  core0.rmd:

    [outputfiel]:

    Upload function seems to be unuseful.

    [core0.rmd]

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    core0.out
    -a
    -boot
    -e _c_int00
    -order=L
    -map core0.mxp
    ROMS
    {
    ROM1: org = 0x0C000000, length = 0x100000, memwidth = 32, romwidth = 32
    files = { core0.btbl }
    }
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    [spiboot.bat]:

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    @echo off
    setlocal
    set IBL_UTIL=C:\ti\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\util
    @REM FOR PROCESSOR SDK RTOS change the path to SDK_INSTALL_PATH\pdk\pdk_c66xx_2_0_0\packages\ti\boot\ibl\src\util
    echo Compilation successful, proceeding with SPI boot setup...
    echo.
    C:\ti\ccsv5\tools\compiler\c6000_7.4.4\bin\hex6x.exe core0.rmd
    %IBL_UTIL%\btoccs\b2i2c core0.btbl core0.btbl.i2c
    %IBL_UTIL%\btoccs\b2ccs core0.btbl.i2c core0.i2c.ccs
    %IBL_UTIL%\romparse\romparse nysh.spi.map
    byteswapccs i2crom.ccs app.dat
    endlocal
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Hex6x execute result, output core.mxp:

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    ********************************************************************************
    TMS320C6x Hex Converter v7.4.4
    ********************************************************************************
    INPUT FILE NAME: <core0.out>
    OUTPUT FORMAT: ASCII-Hex
    PHYSICAL MEMORY PARAMETERS
    Default data width : 8
    Default memory width : 32
    Default output width : 8
    BOOT LOADER PARAMETERS
    Table Address: 0xc000000, PAGE 0
    Entry Point : 0xc10fc20 (_c_int00)
    OUTPUT TRANSLATION MAP
    --------------------------------------------------------------------------------
    0c000000..0c0fffff Page=0 Memory Width=32 ROM Width=32 "ROM1"
    --------------------------------------------------------------------------------
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Chuan Xu
    TI__Mastermind 25535 points

    For Direct SPI boot, I followed the steps given in this FAQ.

    [FAQ] TMS320C6657: How to run the direct SPI-BOOT example on TI-C6657-EVM without IBL ? - Processors forum - Processors - TI E2E support forums

    I am able to locate the memory sections in "spiboot.map" file located at "C6657_directROM_Boot_example\C6657\SPIboot_ddr\src"

    --

    SEGMENT ALLOCATION MAP

    run origin load origin length init length attrs members
    ---------- ----------- ---------- ----------- ----- -------
    008ffd20 008ffd20 00000178 00000178 r--
    008ffd20 008ffd20 00000178 00000178 r-- .emif4Cfg

    -----

      output attributes/
    section page origin length input sections
    -------- ---- ---------- ---------- ----------------
    .emif4Cfg
    * 0 008ffd20 00000178
    008ffd20 00000178 spiboot.obj (.emif4Cfg)

    ---

    GLOBAL SYMBOLS: SORTED BY Symbol Address

    address name
    -------- ----
    00000000 __TI_STATIC_BASE
    00000001 __TI_args_main
    00000400 __TI_STACK_SIZE
    008ffd20 emif4Cfg

    ---

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    ******************************************************************************
    TMS320C6x Linker PC v7.4.24
    ******************************************************************************
    >> Linked Thu Aug 29 12:56:05 2024
    OUTPUT FILE NAME: <spiboot.out>
    ENTRY POINT SYMBOL: "_c_int00" address: 80000680
    MEMORY CONFIGURATION
    name origin length used unused attr fill
    ---------------------- -------- --------- -------- -------- ---- --------
    DDR_CFG 008ffd20 00000180 00000178 00000008 RWIX
    L2MAGIC 008ffffc 00000004 00000000 00000004 RWIX
    DDR 80000000 00002000 00000d0c 000012f4 RWIX
    SEGMENT ALLOCATION MAP
    run origin load origin length init length attrs members
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Regards

    Shankari G

  • 0 in reply to Shankari G
    Prodigy 50 points

    Shankari G,

    It's no problem for the output .map file compile by CCS or makefile, but AFTER execute HEX6X with the .rmd file, problem comes out.

    Here is my output .map file after  compile, which is good.

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    ******************************************************************************
    TMS320C6x Linker PC v7.4.4
    ******************************************************************************
    >> Linked Thu Aug 29 14:35:20 2024
    OUTPUT FILE NAME: <core0.out>
    ENTRY POINT SYMBOL: "_c_int00" address: 0c10fc20
    MEMORY CONFIGURATION
    name origin length used unused attr fill
    ---------------------- -------- --------- -------- -------- ---- --------
    L2SRAM_SYS 00800000 00070000 00022226 0004ddda RW X
    L2_DDR_CFG 00873500 00000100 00000070 00000090 RW X
    L1PSRAM 00e00000 00008000 00000000 00008000 RW X
    L1DSRAM 00f00000 00008000 00000000 00008000 RW
    MSM_IPC 0c000000 00080000 00080000 00000000 RW X
    MSM_SYS0 0c080000 00180000 000b9104 000c6efc RW X
    MSM_APP 0c200000 00200000 00200000 00000000 RW X
    DDR3_SYS0 80000000 08000000 00052b00 07fad500 RW X
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    After executed Hex6x, here is the output .mxp file:------------This is the problem that I'm mentionsed.

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    ********************************************************************************
    TMS320C6x Hex Converter v7.4.4
    ********************************************************************************
    INPUT FILE NAME: <core0.out>
    OUTPUT FORMAT: ASCII-Hex
    PHYSICAL MEMORY PARAMETERS
    Default data width : 8
    Default memory width : 32
    Default output width : 8
    BOOT LOADER PARAMETERS
    Table Address: 0xc000000, PAGE 0
    Entry Point : 0xc10fc20 (_c_int00)
    OUTPUT TRANSLATION MAP
    --------------------------------------------------------------------------------
    0c000000..0c0fffff Page=0 Memory Width=32 ROM Width=32 "ROM1"
    --------------------------------------------------------------------------------
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Chuan Xu
    Prodigy 50 points

    Here is my CCS compiling output files, and the core.rmd is used for hex6x.

    6712.compile_output_files.zip

  • 0 in reply to Chuan Xu
    TI__Mastermind 25535 points

    Chuan Xu,

    Please check the path you set here:- 

    In "Spiboot.bat" file....

    set IBL_UTIL=C:\ti\pdk_c665x_2_0_16\packages\ti\boot\ibl\src\util

    ---

    Post your screenshot and its output when you execute the "spiboot.bat".

    For me all the commands work successfully.

    Regards

    Shankari G

  • 0 in reply to Shankari G
    Prodigy 50 points

    Shankari G

    Shankari G said:
    set IBL_UTIL=C:\ti\pdk_c665x_2_0_16\packages\ti\boot\ibl\src\util

    I'm using C6678, mcsdk_2_01_02_06, pdk_C6678_1_1_2_6. So, the IBL_UTIL is under C:\ti\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\util

     

    Shankari G said:
    Post your screenshot and its output when you execute the "spiboot.bat".

    By the way, the  size of core.out（compiled by CCS）is 11MB, and hex6x output file core.btbl is 2.17MB.(you can see it in the zip). Maybe you can use my items to execute with hex6x, you may got the problem i'm faing now.

    Chuan Xu said:
    6712.compile_output_files.zip

    I think if we should modify the .rmd file, to let Hex6x treat .emif4Cfg as a bootable section? Because, Hex6x only convert the initilized sections according to the SPRUI03B. 

    Thanks !

  • 0 in reply to Chuan Xu
    TI__Mastermind 25535 points
    Chuan Xu said:
    I think if we should modify the .rmd file, to let Hex6x treat .emif4Cfg as a bootable section? Because, Hex6x only convert the initilized sections according to the SPRUI03B. 

    No, I don't think. All these executable files are ready made to be used by the customer.

    --

    Any way Let me check and compare the file sizes of mine with yours.

    Regards

    Shankari G

  • +1 in reply to Shankari G
    TI__Mastermind 25535 points

    Chuan Xu,

    Only the latest processor SDK 6.3 is supported through Forum support.

    There is no support for older packages like MCSDK.

    --

    When I experimented the spiboot.out, the following are the files generated - given with file size ----> You can compare it with your file sizes.

    However, these comparisons need not match as I use the processor SDK 6.3 and you use MCSDk.

     

    I would recommend you to use the latest processor SDK 6.3.

    PROCESSOR-SDK-RTOS-C667x  06_03_00_106
    https://software-dl.ti.com/processor-sdk-rtos/esd/C667x/latest/index_FDS.html

    Regards

    Shankari G

  • 0 in reply to Shankari G
    Prodigy 50 points

    Shankari G

    Thanks Again!

    I was busy with the work recently, I've already solve this by Insert the DDR CFG TABLE into the image directly!

    Post the resolve method:EVM6678LE I2C-Nor flash boot 与 SPI flash boot 的具体操作问题 - 处理器论坛 - 处理器 - E2ETm 设计支持 (ti.com)