AM625: How to configure DDR4 with 2 DDR4 chip of 4GB

Alexis LOGNON

Intellectual 580 points

Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG, , AM623

Tool/software:

Hello,

We upgrade our design to use 8 Giga Bytes of DDR4 using 2 Micron chip MT40A4G8NEA-062E:F.

I used the SDK 09.02 and sysconfig tools online.

Memory Frequency (MHz) 800Mz
Data Bus Width (per device) 8
Density (per device) (Gb) 32

Chip Selects / Ranks 1

Our DDR4 chip are wired with 1 chip select.

1 - Do I need to select 2 for Chip Selects/Ranks to have access to the 8GB of RAM ?

Currently the bootloader u-boot boot only with a density of 8Gb and 16Gb.

When the 32Gb is configure in sysconfig the bootloader freeze and the following trace is displayed.

U-Boot SPL 2023.04-00003-g2ac2a3ccc0-dirty (Oct 28 2024 - 15:17:10 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.7--v09.02.07 (Kool Koala)')
SPL initial stack usage: 13408 bytes
I patch the bootloader u-boot to use 4GB only instead of 8GB, the patch is at the bottom of the thread.
2 - Could you tell me if the patch is correct, and what do you suggest to debug the issue ?
3 - Could you provide me a script which I can use with Code Composer Studio and the JTAG probe ?
Currently the script AddrMapCheck returns: "Total DDR capacity detected = 2GBytes"
Thanks for your help.
Regards,
 
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index 87f6bfccda..2feb2f9490 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -15,8 +15,9 @@
 / {
 memory@80000000 {
 device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
 bootph-pre-ram;
 };
 };
diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts
index acb37d03bd..5b126a877b 100644
--- a/arch/arm/dts/k3-am625-sk.dts
+++ b/arch/arm/dts/k3-am625-sk.dts
@@ -45,8 +45,9 @@
 
 memory@80000000 {
 device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
 
 };
 
diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi
index a350fe2433..7a6580a7a9 100644
--- a/arch/arm/dts/k3-am62x-sk-common.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-common.dtsi
@@ -30,8 +30,9 @@
 
 memory@80000000 {
 device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
 
 };
 
diff --git a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
index df01893669..0374f9a0b9 100644
--- a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
@@ -1,11 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.10.01
- * Thu Apr 25 2024 15:57:40 GMT+0200 (Central European Summer Time)
+ * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Mon Oct 28 2024 14:33:57 GMT+0100 (heure normale d<E2><80><99>Europe centrale)
 * DDR Type: DDR4
 * Frequency = 800MHz (1600MTs)
- * Density: 8Gb
+ * Density: 32Gb
 * Number of Ranks: 1
 */
 
@@ -13,7 +13,8 @@
 #define DDRSS_PLL_FHS_CNT 6
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
-#define DDRSS_SDRAM_IDX 15
+#define DDRSS_SDRAM_IDX 17
+#define DDRSS_REGION_IDX 17
 
 
 #define DDRSS_CTL_0_DATA 0x00000A00
@@ -333,8 +334,8 @@
 #define DDRSS_CTL_314_DATA 0x00000000
 #define DDRSS_CTL_315_DATA 0x00000100
 #define DDRSS_CTL_316_DATA 0x00000000
-#define DDRSS_CTL_317_DATA 0x00000101
-#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_317_DATA 0xFFFFFEFF
+#define DDRSS_CTL_318_DATA 0xFFFF0000
 #define DDRSS_CTL_319_DATA 0x000FFF00
 #define DDRSS_CTL_320_DATA 0xFFFFFFFF
 #define DDRSS_CTL_321_DATA 0x00FFFF00
@@ -516,7 +517,7 @@
 #define DDRSS_PI_74_DATA 0x00000000
 #define DDRSS_PI_75_DATA 0x00000005
 #define DDRSS_PI_76_DATA 0x01000000
-#define DDRSS_PI_77_DATA 0x04010000
+#define DDRSS_PI_77_DATA 0x03FF0000
 #define DDRSS_PI_78_DATA 0x00020000
 #define DDRSS_PI_79_DATA 0x00010002
 #define DDRSS_PI_80_DATA 0x00000001
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 322e8e86de..e2cf90ec8e 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -786,7 +786,7 @@ static int k3_ddrss_probe(struct udevice *dev)
 if (IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM642)) {
 /* AM62x SIP supports only up to 512 MB SDRAM */
 /* AM64x supports only up to 2 GB SDRAM */
- writel((((ilog2(ddrss->ddr_ram_size) - 16) << 5) | 0xF),
+ writel((((ilog2(ddrss->ddr_ram_size) - 16) << 5) | 0x1F),
 ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG);
 writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
 }

5 months ago

0 Nick Saulnier 5 months ago

TI__Guru* 92605 points

For future readers, the concept discussed here is a continuation of this thread:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1387864/am625-how-to-set-up-am625-4gb-ram-on-sdk-9-2

Hello Alexis,

I am sending your thread to our DDR hardware guy to begin. We might need to bounce you around to several different people to get through your questions. Feel free to ping the thread if you do not get another response within a couple of business days.

Regards,

Nick

0 Alexis LOGNON 5 months ago in reply to Nick Saulnier

Intellectual 580 points

Hello,

I encounter issue when setting only 4GB of the 8GB available in u-boot.

The issue is linked with the SDK 09.02, because the same modification doesn't seem to exist in SDK 10.00.

By the way we check our custom design and confirm that only 1 chip select won't allow the CPU to use 8GB of DDR4, only one bank of 2GB of each chipset can be selected.

I going to test the memory with u-boot mtest command to confirm that the 4GB works correctly.

Let me know as soon as youo have news about the previous questions.

Regards,

Alexis.

0 Alexis LOGNON 5 months ago in reply to Alexis LOGNON

Intellectual 580 points

Hi Nick,
Here is my result using u-boot from SDK 10.00.
I don't understand why the upper 2GB are set are "reserved", I didn't reserve this memory area in the device tree.
Should I expect that this memory area will be also seen as "reserved" by the linux kernel ?
Here is the memory section is the file arch/arm/dts/k3-am625-sk.dts:
 memory@80000000 {
 device_type = "memory";
 /* 4G RAM */
 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
 <0x00000008 0x80000000 0x00000000 0x80000000>;
};
Here is the memory section is the file arch/arm/dts/k3-am625-sk-common.dtsi:
 memory@80000000 {
 bootph-pre-ram;
 device_type = "memory";
 /* 4G RAM */
 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
 <0x00000008 0x80000000 0x00000000 0x80000000>;
 };
=> bdinfo 
boot_params = 0x0000000000000000
DRAM bank   = 0x0000000000000000
-> start    = 0x0000000080000000
-> size     = 0x0000000080000000
DRAM bank   = 0x0000000000000001
-> start    = 0x0000000880000000
-> size     = 0x0000000080000000
flashstart  = 0x0000000000000000
flashsize   = 0x0000000000000000
flashoffset = 0x0000000000000000
baudrate    = 115200 bps
relocaddr   = 0x00000000fff05000
reloc off   = 0x000000007f705000
Build       = 64-bit
current eth = ethernet@8000000port@1
ethaddr     = 28:b5:e8:c6:fa:68
IP addr     = <NULL>
fdt_blob    = 0x00000000fded30e0
new_fdt     = 0x00000000fded30e0
fdt_size    = 0x0000000000012ca0
multi_dtb_fit= 0x0000000000000000
lmb_dump_all:
 memory.cnt = 0x2 / max = 0x10
 memory[0]      [0x80000000-0xffffffff], 0x80000000 bytes flags: 0
 memory[1]      [0x880000000-0x8ffffffff], 0x80000000 bytes flags: 0
 reserved.cnt = 0x6 / max = 0x10
 reserved[0]    [0x9c700000-0x9c7fffff], 0x00100000 bytes flags: 0
 reserved[1]    [0x9c800000-0x9d9fffff], 0x01200000 bytes flags: 4
 reserved[2]    [0x9db00000-0x9e6fffff], 0x00c00000 bytes flags: 4
 reserved[3]    [0x9e780000-0x9fffffff], 0x01880000 bytes flags: 4
 reserved[4]    [0xfcecd000-0xffffffff], 0x03133000 bytes flags: 0
 reserved[5]    [0x880000000-0x8ffffffff], 0x80000000 bytes flags: 0
devicetree  = separate
serial addr = 0x0000000002800000
 width      = 0x0000000000000000
 shift      = 0x0000000000000002
 offset     = 0x0000000000000000
 clock      = 0x0000000002dc6c00
arch_number = 0x0000000000000000
TLB addr    = 0x00000000ffff0000
irq_sp      = 0x00000000fded1ff0
sp start    = 0x00000000fded1ff0
Early malloc usage: 3bc0 / 8000
 
=> mtest 0x82000000 0x9CBFFF00 0x12345678 1
Testing 82000000 ... 9cbfff00:
Pattern 0000000012345678  Writing...  Reading...
Tested 1 iteration(s) with 0 errors.
=> mtest 0xA0000000 0xFC5DD000 0x12345678 1
Testing a0000000 ... fc5dd000:
Pattern 0000000012345678  Writing...  Reading...
Tested 1 iteration(s) with 0 errors.
=> mtest 0x880000000 0x8ffffffff 0x12345678 1
Testing 880000000 ... 8ffffffff:
Pattern 0000000012345678  Writing...  Reading...
Tested 1 iteration(s) with 0 errors.
=> mtest 0x82000000 0x9CBFFF00 0x12345678 1

0 JJD 5 months ago in reply to Alexis LOGNON

TI__Guru* 79670 points

Alexis, the MT40A4G8NEA-062E:F device that you are using is a dual rank device. Each package is 8-bit wide. Thus the sysconfig tool should be configured as such:

Data Bus Width (per device) 8
Density (per device) (Gb) 32

Chip Selects / Ranks 2

Ensure that the board connects both CS0 and CS1 signals to both DDR packages. Post the DDR portion of the schematic if you need me to take a look.

Regards,

James

0 Alexis LOGNON 4 months ago in reply to JJD

Intellectual 580 points

Hi James, Nick,

I will wait that our design will be fixed to wire both CS 1 and 2 from the AM62x to the DDR package.

I configured only 4GB at this moment until I receive the new board.

By the way could you confirm that the SDK 10.00 handle correctly the 4GB of RAM, because even if the bootloader u-boot see the 2 banks of 2GB, under Linux I only see 2GB of RAM.

I check the memory mapping in the Linux device tree and it is mapping the 2 bank at 0x8000000 and 0880000000.

Do I need to patch something else ?

Regards,

Alexis.

0 Alexis LOGNON 4 months ago in reply to Alexis LOGNON

Intellectual 580 points

Hi James, Nick,

I can't have the same behaviour of the SDK 08.06, when I change the memory area in the device-tree.

When u-boot shows 2 banks of 2GB, the kernel doesn't reflect the memory configuration set in the kernel device tree.

I modified the files k3-am625-sk.dts and k3-am62x-sk-common.dtsi and load the device tree manually from u-boot.

I tested the following configuration:

    memory@80000000 {
        device_type = "memory";
        /* 1G RAM */
        reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
    };

    memory@80000000 {
        device_type = "memory";
        /* 2G RAM */
        reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
    };

    memory@80000000 {
        device_type = "memory";
        /* 4G RAM */
        reg = <0x00000000 0x80000000 0x00000000 0x80000000>,

<0x00000008 0x80000000 0x00000000 0x80000000>;
};

But none of this configuration is taken in account in the kernel.

cat /proc/meminfo and cat /proc/iomem still show 2GB of RAM for each configuration.

The kernel device-tree memory register are configured as followed:

cat /proc/device-tree/memory@80000000/reg |hexdump

0000000 0000 0000 0080 0000 0000 0000 0080 0000

0000010 0000 0800 0080 0000 0000 0000 0000 0000

Could you tell me how to configure the kernel device tree to get the 4GB of RAM available under Linux in sDK10 ?

Regards,

Alexis.

0 Bin Liu 4 months ago in reply to Alexis LOGNON

TI__Guru**** 153671 points

Hi Alexis,

I didn't closely follow this thread and didn't look into the issue you have, but just wanted to point out that since SDK10.0, the memory node in kernel devicetree does no longer take affect, the memory size in kernel is determined by the corresponding memory node in U-Boot devicetree. After U-Boot initializes DDR , it loads kernel dtb to DDR then modify its memory node to be the same setting as in U-Boot devicetree, then boot the kernel.

Please see the following U-Boot code for reference.

https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/arch/arm/mach-k3/am625_fdt.c?h=10.00.08#n54

0 Alexis LOGNON 4 months ago in reply to Bin Liu

Intellectual 580 points

Hi Bin,

I follow the call tree in u-boot, the function you mentioned is called if the flag ARCH_FIXUP_FDT_MEMORY=y is set.

In my u-boot configuration this flag is set, so the device tree for the kernel is well modified and the section memory ignored in the kernel device tree source.

But I don't understand why only 2GB as shown in the Linux when u-boot show 4GB.

Could you give me more information ?

Could you confirm that the u-boot update the size memory in the device tree memory section ?

So I bypass the issue, by disabling ARCH_FIXUP_FDT_MEMORY to manage directly the memory with the kernel device tree. It would be a better choice to use the fixup code, and not duplicate the memory section in both device tree.

Regards,

Alexis.

0 Bin Liu 4 months ago in reply to Alexis LOGNON

TI__Guru**** 153671 points

Hi Alexis,

I am out of office tomorrow, but I will review the details in this thread once I am back in office to better understand the issue you have, then provide comments.

0 Bin Liu 4 months ago in reply to Alexis LOGNON

TI__Guru**** 153671 points

Hi Alxis,

Alexis LOGNON said:
But I don't understand why only 2GB as shown in the Linux when u-boot show 4GB.

Can you please attach the SDK10.0 uart console log including both U-Boot and kernel boot messages?

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AM625: How to configure DDR4 with 2 DDR4 chip of 4GB