[FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP Design Recommendations / Custom board hardware design – Common queries for PMIC TPS65219 and PDN

HI Board designers, 

Refer below, common queries and replies

Q.1

Our customer has a question about TPS65219. Customer thinks to use TPS6521901 for supplying AM64x power. Is the TPS6521901 programmable device? Or, Is TPS6521901 not programmable device and customer cannot change anything of the output voltage and power sequence? If customer wants to change the power sequence, does customer needs to use TPS6521905? Customer worries about the unintentional change of power sequence. So, customer is happy if TPS6521901

 The TPS6521901 and TPS6521905 both have NVM that can be reprogrammed. It is not easy to accidentally reprogram the NVM, so I do not think the customer needs to worry about accidentally modifying the power sequence. 

The TPS6521905 comes with default setting with all outputs disabled, so it is helpful if a customer wants to program the device on the PCB while keeping all of the outputs in a safe state. 

  Q.2

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1407703/am625-pmic_lpm_en0-connection

Connecting the PMIC_LPM_EN0 to the PMIC MODE/STBY pin is optional. The TPS6521904 NVM has the MODE/STBY pin configured to select the Bucks switching mode with the following polarity:

• MODE/STBY High, Bucks operate in forced-PWM
• MODE/STBY Low, Bucks operate in auto-PFM. 

If you are planning to use an AM62x low power mode where internal processor domains are turned-OFF while all the PMIC rails stay ON, then driving the MODE/STBY pin low with the PMIC_LPM_EN0 will allow to increase efficiency at light load. 

 Q.3

(+) AM625: How to set correct VDD_CORE & VDDA_DDR_PLL0 for LPDDR4 - Processors forum - Processors - TI E2E support forums

TPS6521908 is another option for customers who want to supply VDD_CORE with 0.85V instead of 0.75V. As noted in the processor datasheet, VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is operating at 0.85V. In this scenario, we don't need to configure an LDO in the PMIC to supply 0.85 because Buck1 can supply both. This is why LDO2 is disabled. 

Q.4

(+) TPS65219: 3.3V no output - Power management forum - Power management - TI E2E support forums

The TPS65219 PMIC executes two residual voltage checks; the first one occurs before the power-up sequence is executed and a second occurs during the power-up sequence (right before each rail is turned ON).

The first check can be disabled by changing register field "Register field "BYPASS_RAILS_DISCHA RGED_CHECK" but the second one cannot be disabled. Please note that changing any register field would require to turn-ON the PMIC first and get the device in Active state to enable I2C communication. 

we found out where the residual voltage is coming from. This is come from E-PHY 

- Residual voltage VLDO4 , 2.5V line : 4~500mV /  VDDIO, 3.3V line : 50mV. 

If the backfeeding issue on VLDO4 exist before the PMIC executes the power-up sequence, then none of the rails will turn-ON. The reason is because as I mentioned in my previous message, the PMIC performs the first residual voltage check before executing the power-up sequence.  

Do you see a voltage on VLDO4 before Buck2 is turned ON?

TPS65219: Residual Voltage checks during start-up

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1434550/faq-am625-am623-am625sip-am620-q1-am625-q1-design-recommendations-ustom-board-hardware-design-common-queries-for-pmic-tps65219

Regards,

Sreenivasa

HI Board designers, 

Refer additional inputs

Q.5

TPS6521905: NVM programing procedure

https://www.ti.com/lit/ug/slvucm5/slvucm5.pdf

 Q.6

(+) TPS65219: Can the maximum load capacitance of the channels be exceeded? - Power management forum - Power management - TI E2E support forums

If the maximum output capacitance on the PMIC rails is exceeded, the phase margin starts to drop and stability gets affected.

Just for reference, the TPS65219 PMIC has an option for "multi-PMIC operation" that allows to fully synchronize the sequencing between multiple TPS65219 devices. This feature might help to split the load/POL capacitance across the PMIC rails. Is this a non-automotive application? The TPS65215 has a 4x4mm package option that helps to keep the overall power solution small even when using 2x TPS65219 devices.  

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1204248/tps65219-reprogramming-the-tps65219

 This is a great feature in the TPS65219 PMIC that allows synchronizing multiple devices to power processors and SoCs that require multiple rails! Here is some information for the multi-PMIC operation, feel free to let us know if you have any questions and we will be happy to help.

• GPIO (pin#16) is used to synchronize the two PMICs. 
• To configure the GPIO pin for multi-PMIC, register field "MULTI_DEVICE_ENABLE" must be changed to 1.
• The GPIOs on both PMICs should be tied together sharing the same pull-up resistor.  
• The I2C address for the 2nd PMIC must be changed on register field "I2C_ADDRESS" so they can both be connected to the same I2C bus without conflict. 

 Q.7 TPS65219: Share 3.3V rail for 2pcs AM2434 and peripherals

 If the customer wants to use a single 3.3V rail to supply both MCUs and peripherals, then I would recommend using the TPS6521904 NVM instead.

Here are the two options when using TPS6521904:

• Using 3.3V pre-regulator to supply the 2x TPS6521904 PMICs and an external 3.3V power-switch. The power-switch can be enabled by the PMIC GPO2. The output of the power-switch can supply the MCU 3.3V IO and peripherals.
• Using a 5V pre-regulator to supply the 2x TPS6521904 PMICs and an external 3.3V BUCK. The external Buck can be enabled by the PMIC GPO2. The output of the external 3.3V buck can be used to supply the PMIC LDO1, MCU 3.3V IO and peripherals. 

Regards,

Sreenivasa

HI Board designers, 

Refer additional inputs

Checklist and guidelines for PMIC

https://www.ti.com/lit/zip/slvafe2

Regards,

Sreenivasa

HI Board designers, 

Refer below additional inputs: 

TPS65219: Residual Voltage checks during start-up

ttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1229202/tps65219-residual-voltage-checks-during-start-up

The TPS65219 PMIC performs a voltage check and discharge on each of its power rails to make sure they are all under the SCG threshold before executing the power-up sequence. 

Although not recommended, this safety feature could be bypass by changing the register field "BYPASS_RAILS_DISCHARGED_CHECK" on address 0x1E. Since there is no I2C communication in Initialize state, PMIC would have to be programmed from factory to bypass the discharge check during power-up/power-down sequence. Any custom NVM configuration requires a new orderable part number and approval from our marketing team. 

TPS65219: Programming NVM using the processor itself

(23) TPS65219: Programming NVM using the processor itself - Power management forum - Power management - TI E2E support forums

TPS65219: Difference between TPS65219 and TPS65220

(23) TPS65219: Difference between TPS65219 and TPS65220 - Power management forum - Power management - TI E2E support forums

TPS65220 is designed to operate over extended temperature range.

Regards,

Sreenivasa

Hi Board designers

Input regarding selection of PMIC:

The recommend PMIC(s) on the product folder or used on the SK or EVM schematics has been designed considering the power sequencing, supply rail output slew, nRSTOUT (reset output) delay output from PMIC connected to MCU_PORz after all the supplies ramp for clock to be stable and the sizing of the supply rails based on the processor worst case current draw.

When choosing an alternate non-TI PMIC, the recommendation for custom board designers is to review the relevant collaterals including the data sheet and Maximum Current Ratings document and follow the requirements/recommendations. The recommendation is to review the slew rate requirements, Power-up and power-down sequence sections of the data sheet and confirm the non-TI PMIC based power architecture follows the recommendation.

An important point to note is the processor does not support dynamic scaling of the core voltage or the analog supplies.

Inputs regarding supply decay

Refer below FAQ

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1485094/faq-am62a7-power-rails-decay-note-in-latest-datasheet/5703704#5703704

I have placed the note in both sections because it applies to both power-up and power-down. The power-up sequence should not begin until all power rails are below 300mV, and the power-down sequence is not complete until all power rails are below 300mV.

Regards,

Sreenivasa

HI Board designers, 

Inputs on power supply sizing:

Using Maximum Current Ratings application note vs Power Estimation Tool PET 

The max current app note is representing the current draw for a group of rails. Please note that it is not expected for this current to necessarily be replicated in the power estimation tool. The PET will tend to show more average use case power while the max current app note is intended to be used for power supply sizing as it will allow for the max transient on these groups with some margin. The PET should not be used for power supply sizing.

Regards,

Sreenivasa

Hi Board designers, 

PMIC capacitor and feedback recommendations

PMIC - feed back and jumper or 0R provisioning 

Regards,

Sreenivasa

Hi Board designers,

Refer below inputs for PMIC power sequencing.

AM6421: Sudden Loss of Power Impact on Power Down Sequence

(+) AM6421: Sudden Loss of Power Impact on Power Down Sequence - Processors forum - Processors - TI E2E support forums

 As stated in the AM64x datasheet, "The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE + 0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after VDDR_CORE when VDD_CORE is operating at 0.75V". AM64 was characterized under operating conditions so we cannot guarantee the expected operation beyond the conditions specified in the datasheet. PCB designers are responsible for validating and characterizing the SoC under specific use case conditions to confirm it meets the application system level requirements. 

Handling uncontrolled power-down requires additional considerations in the design like adding additional input capacitance or a discrete supervisor to monitor voltage at the power source and trigger an OFF request before PMIC loses power. Here is an example FAQ for reference: https://e2e.ti.com/blogs_/b/powerhouse/posts/how-to-meet-power-sequencing-requirements-with-a-pmic.

Another option to consider to mitigate the sequencing concerns during uncontrolled power-down is running the main CORE at 0.85V which allows to combine VDD_CORE and VDDR_CORE together. In this scenario both rails are supplied by the same PMIC DCDC regulator.

Regards,

Sreenivasa

Hi Board designers,

E2E for reference

(32) AM620-Q1: MCU Rail Definition in Voltage/Power/Clock Domain - Processors forum - Processors - TI E2E support forums

(32) AM620-Q1: Power Consumption Optimization For MCU Only mode (or deep sleep mode) - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hi Board designers,

Information related to open drain GPO

Regards,

Sreenivasa

Hi Board designers, 

Inputs related to user programmable PMIC 

In case User-programmable power management IC (PMIC) is required, TPS6521905 with three step-down DC/DC converters and four LDOs can be considered.
Dynamic scaling of supplies is not allowed for the processor family.

https://www.ti.com/product/TPS6521905

Regards,

Sreenivasa

Hi Board designers, 

Refer below input related to eFuse caps and pinout

TPS22918 5.5-V, 2-A, 52-mΩ On-Resistance Load Switch

Regards,

Sreenivasa