TDA4VEN-Q1: custom kernel implementation::img_proc

Hi,

Could you write the output of the preproc node and check if you are getting the expected output. Please note that the input to the TIDL node should match with your model expectations such as the input size, tensor datatype etc.

Regards,

Nikhil

Hi sir,

Yes I have taken care of the parameters like input size,tensor datatype. 

The model expects int_16 tensor datatype, 224x224 RGB planar. I have taken these parameters into consideration for the custom pre-processing logic.

Thanks,

Raju.

Hi Raju,

In this case, there should not be an error in the output, if parameters such as (padding, mean, scale etc) are taken care.

Can you dump the output of pre-proc and confirm that the data values are as expected?

Do you have a reference value for the input to the TIDL node, which would give correct output from the node?

Regards,

Nikhil

 Hi sir,

As part of debugging, I integrated my custom pre-proc kernel in demo app_tidl_od application in 8.2 SDK. As the model size is 1024x512, I adjusted the custom logic to give 1024x512 BGR planar output. I dumped pre-proc output in both cases, one with SDK's preproc and other with custom logic.

When I dumped with sdk's pre-proc, I found the tenosr width and height as 1025 and 515. I assume it is due to the padding. I dumped the pre-proc outpur for one frame and checked the pattern. I could not understand the way of padding. 

Please guide me how could I change my custom logic with respect to this?

Thanks,

Raju

Hi sir,

We have found a source file vx_dl_pre_proc_target_no_dma.c avaible in SDK 10.1 at $vision_apps/kernels/img_proc/c66 and ported to a new custom kernel for pre-processing on C7x core. When this node is integrated in the demo application app_tidl_od( SDK 8.2) running on J721E, the application is giving proper bounding boxes on the display.When the same node is integrtaed in SDK 10.1 in our custom file based application, the pre-processing node is not giving expected outupt.

Note:

1)Custom pre-proc kernel is built on C7x core in both SDK 8.2 and 10.1

2)In the 8.2 SDK, eventhough the detections are proper on the display, I have verified the pre-proc dump using VOOYA app, it is not coming as expected.

3)In the experiment done with J721E, the reference application is "app_tidl_od" where the input resolution is 1024x512 whereas J722S experiment has our custom application where tidl expects 224x224, thats the reason you observed the size change in below attached files but output are from the same input YUV image.

Please find the pre-proc dump in both SDK 8.2(J721E) and 10.1(J722S) respectively.

Please provide any reliable source code available in SDK 10,1 for pre-processing(NV12->RGB) that can be ported on to J722s as there are no working demo available on J722S which has pre-processing module.

Thanks and Regards,

Raju

Hi sir,

Gentle reminder about the response!!

As we dont have preprocessing node validated on J722s, we would like to know the expected output from the preproc node. Is it same like J721E, a tensor( NCHW RGB/BGR planar) or different?

Please confirm this as well.

Thanks,

Raju.

Hi sir,

Could you please respond, as it is very important for our project.

Thanks,

Raju.

Hi sir,

Any update regarding the below requirement,

"Please provide any reliable source code available in SDK 10.1 for pre-processing(NV12->RGB) that can be ported on to J722s as there are no working demo available on J722S which has pre-processing module".

Thanks,

Raju.