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TDA4AL-Q1: Failed to start CCS after loadJSFile launch.js, stop at J721S2 Running the DDR configuration... Wait till it completes!

Part Number: TDA4AL-Q1
Other Parts Discussed in Thread: SYSCONFIG, TDA4VL

Tool/software:

Dear TI

We would like to use CCS to run .out file to check 

However, we stop at the "J721S2 Running the DDR configuration... Wait till it completes!"

and have following error log

Do you have any comment?

We use pdk_j721s2_10_01_00_25 and with 8GB DDR memory(mt53e2g32d4de-046)

https://tw.micron.com/products/memory/dram-components/lpddr4/part-catalog/part-detail/mt53e2g32d4de-046-aut-c

TI's default design seem 16GB, 

Should I need to do some modification and rebuild about sciclient_ccs_init_mcu1_0_release.xer5f and sciserver_testapp_freertos_mcu1_0_release.xer5f?

Thank you very much

  • Hi,

    and have following error log

    Seems like your DDR device might differ from the TI EVM? For custom board, have you used DDR tool to re-generate DDR configuration? if no, use the SYSCONFIG tool, DDR configuration for TDA4AL,  Also please note that launch.js script should be used in no-boot mode. 

    SYSCONFIG IDE, configuration, compiler or debugger | TI.com

    https://www.ti.com/tool/SYSCONFIG 

    Regards,

    Karthik

  • Dear Karthik

    DDR device might differ from the TI EVM?

    Yes, The EVM seem 16GB, we use 8GB and 1GB DDR

    use the SYSCONFIG tool, DDR configuration for TDA4AL

    Which item need to modified and which file need to use

    Thank you very much

  • Hi Daniel,

    Which item need to modified and which file need to use

    All of the details you see in the image is the default j721s2 EVM DDR configuration; please alter it according to your DDR. After updating, the board_ddrRegInit.h file will be updated as well, therefore use the updated file in your SDK.

    Regards,

    Karthik

  • Dear Karthik

    Thank you very much

    after board_ddrRegInit.h file. i need to rebuilf following files only, right?

  •  Dear Karthik

    We stop at this process

    I had chenge the MULTI_DDR_CFG_INTRLV_SIZE of J721S2-DDR-EVM-LP4.gel to J721S2-DDR-EVM-LP4-2132.gel and J721S2-DDR-EVM-LP4-4266.gel of ccs1281\ccs\ccs_base\emulation\gel\J721S2_TDA4VL\J7AEP_DDR_SI

    It is not work

    Failed at "CORTEX_M4F_0: GEL Output: --->>> Waiting for frequency change requests ... <<<---"

    we use this two DDR

    8G : MT53E2G32D4DE-046 AITA

    MT53E2G32D4DE-046 AITA.pdf

    1G : MT53E256M32D1KS-046 AUTL

    1768.z41m_automotive_lpddr4x_lpddr4_MT53E256M32D1KS-046 AUTL.pdf

  • Hi Daniel,

    Could you share with me the files listed below?

    J7_DDR_Config.gel
    launch.js
    board_ddrRegInit.h


    Regards,

    Karthik

  • Dear Karthik

    Do you have any update?

  • Dear Karthik

    Do you have any update?
    Please help to check the attached files

    Thank you veyr much

  • Hi Daniel,

    8G : MT53E2G32D4DE-046 AITA

    MT53E2G32D4DE-046 AITA.pdf

    1G : MT53E256M32D1KS-046 AUTL

    Since you are using two DDRs, we need to review the DDR design. Would you kindly share your schematic with us?

    Regards,

    Karthik

  • Dear Karthik

    We plan use two kind of DDR, 

    Sofsar, the 8GB device can bootup normally with MCU SPL after reference following URL

    However, it NOT be used by CCS normally

    I think it should not have HW/schematic  issue

    Are there any issue about my J7_DDR_Config.gel/launch.js/board_ddrRegInit.h ?

    the attached file is schematic  about DDR.

    Please help to check it

    EAGLEYE_S01_20241129_0900_DDR4.pdf

  • Hi Daniel,

    You are using just a single DDRSS, correct? (that is what it appears from your schematic).

    From your update on April 10th, it appears the GELs are trying to initialize DDRSS1 (setting PLL26 which corresponds to DDRSS1); however, it should not initialize DDRSS1 if there is no memory attached.

    The J721S2 GELs have a bug and need the following update (on right side below) to support a single DDRSS:

    Can you try making the changes above to prevent the GELs from trying to initialize DDRSS1?

    You will also need to make sure that in your DDR register configuration file (generated from the SYSCONFIG) tool, you have selected just a single DDRSS (DDRSS0) for tool input parameter "DDR Controllers Utilized in System".

    Regards,
    Kevin

  • I connect XDS110 at  TDA4AL 1GB DDR board, with J7_DDR_Config_1GB.gel modified as you suggest 
    how can I modify the gel file for correct DDR setting ?

    js:> loadJSFile "C:\src\0506\launch.js"
    Connecting to Cortex_M4F_0!
    Fill R5F ATCM memory...
    Writing While(1) for R5F
    Loading TIFS Firmware ... c:/ti/j7presi/workarea/pdk/packages/ti/drv/sciclient/soc/sysfw/binaries/ti-fs-firmware-j721s2-gp.bin
    TIFS Firmware Load Done...
    TIFS Firmware run starting now...
    J721S2 Running the DDR configuration... Wait till it completes!
    Error evaluating "J7_LPDDR4_Config_Late()": Target failed to read 0x80114080
    at (*((unsigned int*) (0x80000000U+fsp_clkchng_req_addr))&0x80) [J7_DDR_Config.gel:3337]
    at DDRSS_LPDDR4_Ack_Freq_Upd_Req(ddrss_num) [J7_DDR_Config.gel:3413]
    at J7_LPDDR4_Config_Single(0) [J7_DDR_Config.gel:3699]
    at J7_LPDDR4_Config() [J7_DDR_Config.gel:3734]
    at J7_LPDDR4_Config_Late() (C:\src\0506\launch.js#130)
    js:>


    CORTEX_M4F_0: GEL Output: Configuring ATCM for the R5Fs
    CORTEX_M4F_0: GEL Output: ATCM Configured.
    CORTEX_M4F_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
    CORTEX_M4F_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
    CORTEX_M4F_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
    CORTEX_M4F_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
    CORTEX_M4F_0: GEL Output: This is consistent with the SoC DV assumptions.
    CORTEX_M4F_0: GEL Output: R5F Halt bits set.
    CORTEX_M4F_0: GEL Output: C71X_x DSPs configured for Wait In Reset Mode
    CORTEX_M4F_0: GEL Output: Debugging disabled.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Checking LPSC_WKUPMCU2MAIN
    CORTEX_M4F_0: GEL Output: Power Domain: On
    CORTEX_M4F_0: GEL Output: Module State: Enable
    CORTEX_M4F_0: GEL Output: Programming all PLLs.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 0 (Main PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 0 (Main PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 3 (CPSW5X PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 3 (CPSW5X PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 4 (Audio 0 PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 4 (Audio 0 PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 5 (Video PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 5 (Video PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 7 (MSMC PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 7 (MSMC PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 16 (DSS0 PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 16 (DSS0 PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 17 (DSS1 PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 17 (DSS1 PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 19 (DSS3 PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 19 (DSS3 PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 25 (Vision PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 25 (Vision PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
    CORTEX_M4F_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming MCU PLL 1 (MCU Peripheral PLL)
    CORTEX_M4F_0: GEL Output: MCU PLL 1 (MCU PLL) Set.
    CORTEX_M4F_0: GEL Output: Programming MCU PLL 2 (MCU CPSW PLL)
    CORTEX_M4F_0: GEL Output: MCU PLL 2 (MCU PLL) Set.
    CORTEX_M4F_0: GEL Output: All PLLs programmed.
    CORTEX_M4F_0: GEL Output: Powering up all PSC power domains in progress...
    CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_ALWAYSON
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DMSC
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DEBUG2DMSC
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_GPIO
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN2WKUPMCU
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_TEST
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_DEBUG
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_MCAN_0
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_MCAN_1
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_OSPI_0
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_OSPI_1
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_HYPERBUS
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_I3C_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_ADC_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_ADC_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_SPARE_0 (HSM)
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_R5_0
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_R5_1
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_PULSAR_PBIST_0
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_ALWAYSON
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_TEST
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_PBIST
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_AUDIO
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_ATL
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MLB
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MOTOR
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MISCIO
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_GPMC
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_VPFE
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_VPE
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_1
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_DEBUG
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_2
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC4B_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC4B_1
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC8B_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_SAUL
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_I3C
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_SERDES_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_2
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_3
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_4
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_5
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_6
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_7
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_8
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_9
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_10
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_11
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_12
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_13
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DSS_PBIST
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DSS
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_TX_DPHY_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DSI
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_EDP_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_CSITX_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_PHY_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_PHY_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_CSITX_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_TX_DPHY_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DSI_1_PBIST
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PCIe_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_0
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_1
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_2
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_3
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powered up all Main Timers.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_2
    CORTEX_M4F_0: GEL Output: No change needed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_0_PBIST
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_1_PBIST
    CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
    CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_0_PBIST
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUCOM
    CORTEX_M4F_0: GEL Output: Timeout Error. State not changed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUPBIST
    CORTEX_M4F_0: GEL Output: Timeout Error. State not changed.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUCORE
    CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_PBIST
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_PBIST
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_1
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_1_PBIST
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DMPAC
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_SDE
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_DMPAC_PBIST
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC_PBIST
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up LPSC_CPSW_2
    CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
    CORTEX_M4F_0: GEL Output: Powering up all PSC power domains done!
    CORTEX_M4F_0: GEL Output: MCU R5F Cluster set to split mode.
    CORTEX_M4F_0: GEL Output: Main R5F Cluster 0 set to split mode.
    CORTEX_M4F_0: GEL Output: Main R5F Cluster 1 set to split mode.
    CORTEX_M4F_0: GEL Output: --->>> ================================================== <<<---
    CORTEX_M4F_0: GEL Output: --->>> Set DDR Interelave Configuration: <<<---
    CORTEX_M4F_0: GEL Output: --->>> multi DDR config 0 : 0x0x000B0003 <<<---
    CORTEX_M4F_0: GEL Output: --->>> multi DDR config 1 : 0x0x00000003 <<<---
    CORTEX_M4F_0: GEL Output: --->>> Dual DDR enabled <<<---
    CORTEX_M4F_0: GEL Output: --->>> 128B Granule Size <<<---
    CORTEX_M4F_0: GEL Output: --->>> ================================================== <<<---
    CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<---
    CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to 20MHz/19.2MHz on silicon (bypass)
    CORTEX_M4F_0: GEL Output: Set DDR0 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
    CORTEX_M4F_0: GEL Output: --->>> DDR0 controller programming in progress.. <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 controller programming completed... <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PI programming in progress.. <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PI programming completed... <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 0 programming in progress.. <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 0 programming completed... <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 1 programming in progress.. <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 1 programming completed... <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 2 programming in progress.. <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 2 programming completed... <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 3 programming in progress.. <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 3 programming completed... <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Address slice 0 programming in progress.. <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Address Slice 0 programming completed... <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY programming in progress.. <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY programming completed... <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR PI initialization started... <<<---
    CORTEX_M4F_0: GEL Output: --->>> DDR Controller initialization started... <<<---
    CORTEX_M4F_0: GEL Output: --->>> Waiting for frequency change requests ... <<<---
    CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
    CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz.
    CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
    CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.

  • launch.js , J7_DDR_Config_1GB.gel at this link
    drive.google.com/.../view