Hi Board Designers, 

Refer below inputs:

Available GPIO instances 

AM64x/AM243x
Signal Descriptions
GPIO
MAIN Domain Instances
GPIO0 Signal Descriptions

GPIO0_0 ... GPIO0_86
GPIO1 Signal Descriptions

GPIO1_0...GPIO1_79
MCU Domain Instances
MCU_GPIO0 Signal Descriptions

MCU_GPIO0_0...MCU_GPIO0_22

AM62x

GPIO
MAIN Domain
GPIO0 Signal Descriptions

GPIO0_0...GPIO0_91
GPIO1 Signal Descriptions

GPIO1_0...GPIO1_51
MCU Domain
MCU_GPIO0 Signal Descriptions

MCU_GPIO0_0...MCU_GPIO0_23

References for interrupt 

4.7 General Connectivity
4.7.1 General Purpose Input/Output (GPIO)
This section contains the integration details for the GPIO modules on this device. For Further information, see
the General Purpose Interface section of the Peripherals chapter

10.1.5 GPIO Interrupt Handling
There are three GPIO modules in the device, which could generate almost 200 interrupts. Those GPIO interrupt
outputs are routed to the GPIO interrupt router first before they are routed to the final interrupt destination. The
GPIO interrupt router allows each output to select each GPIO interrupt independently.

Table 10-9. GPIO_mux_introuter Connection

Bank and individual registers

12.2.1 General-Purpose Interface (GPIO)
This chapter describes the General-Purpose Input/Output (GPIO) for the device.
12.2.1.1 GPIO Overview
The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an output, the user can write to an internal register to
control the state driven on the output pin. When configured as an input, user can obtain the state of the input by
reading the state of an internal register.
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different
interrupt/event generation modes.
The device has one or more instances of GPIO modules. The GPIO pins are grouped into banks (16 pins
per bank and 9 banks per module), which means that each GPIO module provides up to 144 dedicated
general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 432
(3 instances × (9 banks × 16 pins)) pins. Since MCU_GPIO0_[23:143], GPIO0_[87:143], and GPIO1_[88:143]
are reserved in this device, general purpose interface supports up to 198 pins.
Signal Descriptions

12.2.1.4.4 GPIO Interrupt Connectivity
Because this device muxes GPIO signals with other functional signals, the availability of any particular GPIO and
hence the usability of its associated interrupt will change based on the use case pin muxing. The large number
of possible GPIO interrupt sources makes it impractical to route all interrupt events to each processing element.
Since most applications do not typically require a large number of GPIO interrupts, the interrupt uncertainty
is resolved by mapping all GPIO interrupts to a series of event muxes implemented using Interrupt Router
(IntRouter) modules. These muxes allow any one of the available GPIO interrupts to be selected and passed
on as an event to the various processor interrupt controllers and DMA controllers. Event selection is controlled
through associated registers within each IntRouter.
The GPIO bank interrupts already represent a consolidation of the 16 GPIO interrupts associated with each bank
and are routed directly to various interrupt controllers rather than through the GPIO IntRouters.
One of the GPIO pins has a potential use case as an Arm reset input and should therefore be routed as highest
priority interrupt in the GIC and mapped to nFIQ in software.

AM62Ax/AM62Dx
Signal Descriptions
GPIO
MAIN Domain Instances
GPIO0 Signal Descriptions

GPIO0_0...GPIO0_91
GPIO1 Signal Descriptions

GPIO1_0...GPIO1_51
MCU Domain Instances
MCU_GPIO0 Signal Descriptions

MCU_GPIO0_0...MCU_GPIO0_23

AM62D-Q1

4.8 General Connectivity
4.8.1 General Purpose Input/Output (GPIO)
This section contains the integration details for the GPIO modules on this device. For Further information, see
the General Purpose Interface section of the Peripherals chapter

10.1.3 GPIO Interrupt Handling
There are three GPIO modules in the device, which could generate almost 200 interrupts. Those GPIO interrupt
outputs are routed to the GPIO interrupt router first before they are routed to the final interrupt destination. The
GPIO interrupt router allows each output to select each GPIO interrupt independently.

The two GPIO modules in the Main domain use one GPIO interrupt router while the GPIO
module in MCU domain has its own dedicated GPIO router. See Figure 10-7. See also
MAIN_GPIOMUX_INTROUTER0_INTERRUPT_MAP and MCU_GPIOMUX_INTROUTER0_INTERRUPT_MAP

10.5.1.11 MAIN_GPIOMUX_INTROUTER0 Interrupts (AM62D)

12.2.1 General-Purpose Interface (GPIO)
This chapter describes the General-Purpose Input/Output (GPIO) for the device.
12.2.1.1 GPIO Overview
The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an output, the user can write to an internal register to
control the state driven on the output pin. When configured as an input, user can obtain the state of the input by
reading the state of an internal register.
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different
interrupt/event generation modes.
The device has one or more instances of GPIO modules. The GPIO pins are grouped into banks (16 pins
per bank and 9 banks per module), which means that each GPIO module provides up to 144 dedicated
general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 432
(3 instances × (9 banks × 16 pins)) pins. Not all GPIO pins are pinned out. See General Purpose Input/Output
(GPIO) in the Module Integration section for more information.

12.2.1.4.3 Interrupt and Event Generation

12.2.1.4.3 Interrupt and Event Generation
Each GPIO pin (GPj) can be configured to generate a host CPU interrupt (GPINTj) or a synchronization event
to the DMA (GPINTj). Configuration is on per-bank basis. Each bit of the BINT_EN parameter dictates YES/NO
option for each bank. Bit 0 controls bank 0, bit 1 controls bank 1, and so on.
The interrupt and DMA event can be generated on the rising-edge, falling-edge, or on both edges of the GPIO
signal. The edge detection logic is synchronized to the GPIO peripheral clock.
The direction of the GPIO pin does not need to be input when using the pin to generate the interrupt or DMA
event. When the GPIO pin is configured as input, transitions on the pin trigger interrupts or DMA events. When
the GPIO pin is configured as output, software can toggle the GPIO output register to change the pin state and in
turn trigger the interrupt or DMA event.
Note that the direction of the pin need not be input for interrupt generation to work. When the GPINT pin
is configured as input, transitions on the pin trigger interrupts. When the GPINT pin is configured as output,
firmware can toggle the GPIO output register to change the pin state, and in turn trigger interrupts.
Each interrupt output of GPINT signal are available at the module boundary. Each group of 16 GPINT signals
also has their masked interrupt outputs ORed together to generate a per bank interrupt, available at the module
boundary. The idea is to either connect individual interrupts or per bank interrupts to the system interrupt
controller.
12.2.1.4.3.1 Interrupt Enable (per Bank)
The GPIO_BINTEN register provides interrupt enable/disable feature for each bank of 16 GPINT signals.

12.2.1.4.3.2 Trigger Configuration (per Bit)
Two internal registers, RIS_TRIG and FAL_TRIG, specify which edge of the GPj signal generates an interrupt
or DMA event. Each bit in these two registers corresponds to a GPj pin.

12.2.1.4.4 GPIO Interrupt Connectivity

Because this device muxes GPIO signals with other functional signals, the availability of any particular GPIO and
hence the usability of its associated interrupt will change based on the use case pin muxing. The large number
of possible GPIO interrupt sources makes it impractical to route all interrupt events to each processing element.
Since most applications do not typically require a large number of GPIO interrupts, the interrupt uncertainty
is resolved by mapping all GPIO interrupts to a series of event muxes implemented using Interrupt Router
(IntRouter) modules. These muxes allow any one of the available GPIO interrupts to be selected and passed
on as an event to the various processor interrupt controllers and DMA controllers. Event selection is controlled
through associated registers within each IntRouter.
The GPIO bank interrupts already represent a consolidation of the 16 GPIO interrupts associated with each bank
and are routed directly to various interrupt controllers rather than through the GPIO IntRouters.
One of the GPIO pins has a potential use case as an Arm reset input and should therefore be routed as highest
priority interrupt in the GIC and mapped to nFIQ in software.

AM62Px
Signal Descriptions
GPIO
MAIN Domain Instances
GPIO0 Signal Descriptions

GPIO0_0...GPIO0_91
GPIO1 Signal Descriptions

GPIO1_0...GPIO1_51
MCU Domain Instances
MCU_GPIO0 Signal Descriptions

MCU_GPIO0_0...MCU_GPIO0_23

AM62L
Signal Descriptions
GPIO
MAIN Domain Instances
GPIO0 Signal Descriptions

GPIO0_0...GPIO0_99
WKUP Domain
WKUP_GPIO0 Signal Descriptions

WKUP_GPIO0_0...WKUP_GPIO0_6

Related Queries

LVCMOS VIH/VIL

The datasheet states output voltage level of LVCMOS as follows.

 1.8V mode:

VOL     0.45V max.                 @ IOL=3mA

VOH     VDD-0.45V min.          @ IOH=3mA

3.3V mode:

VOL     0.4V max.                   @ IOL=5mA

VOH     2.4V min.                   @ IOH=9mA

AM62P LVCMOS connects to a CMOS buffer fewer current ,e.g. 100uA, would be expected, in general.

Is there any definition by small current available in order to have lower VOL and higher VOH ?

If yes, it might contribute to flexible device selection.

Answers

We recommend customer to use the IBIS model and perform simulation for any current lower than the data sheet recommended value to derive the voltage level.

The customer will need to use the IBIS model of the output buffer in a simulation with the reduced load to determine the VOL and VOH values for their operating condition.

What I am asking is if TI can provide guaranteed VOL and VOH with lower current than datasheet value.

There are no plans to provide any other data points in the datasheet. It is not possible for TI to know the DC load applied to each output buffer of every customer's AM62Px system design. Therefore, we only define the minimum Low Level Output Current and High Level Output Current for which the device is able to maintain the specified VOL and VOH values.

AM62P pin status during reset

This is described in the "BALL STATE DURING RESET RX/TX/PULL:" and "BALL STATE AFTER RESET RX/TX/PULL:" at the beginning of the Pin Attributes section.  The first value represents the state of input buffer, the second value represents the state of the output buffer, and the third value represents the state of internal

The datasheet defines the value of "Off" as shown below:

• TX (Output buffer)
– Off: The output buffer is disabled.
– Low: The output buffer is enabled and drives VOL.

So yes, the pin will be HI-Z when the output buffer is disabled.

From the AM62Px device perspective, you do not need to do anything to these pins as long as they remain in this state. There is no issue until software enables the input buffer. However, you must never allow any AM62Px pin which has its input buffer enabled to float, to a mid-supply potential. This can damage the input buffer when it spends too much time in the mid-supply region. Pins which have their input buffer enabled, should have a steady-state potential that is less than VILSS or greater than VIHSS, and toggle quickly between valid logic states. 

Note: There are a few AM62Px pins which have their input buffer enabled by default. For example, the boot mode inputs. These pins require external pulls to hold them in a valid logic state as soon as power is applied.

Note: Devices attached to the AM62Px pins may require external pulls to hold their pins in a valid logic state. This is unique to each system design, so the system designer will need to evaluate the correct implementation for their system.

Unused pin Default State

The default configuration disables both the receiver and the transmitter in the IO

The input buffer is turned off, the output buffer is disabled, and internal pulls are turned off for most of the device pins by default. This is done because most of these pins have multiple signal functions, and we never know how they are going to be used. The ESD circuits are still attached to the pin, but our ESD circuits are only design to protect the device before and during PCB assembly. ESD performance is only based on human body models and charged device models that represent a typical person or machine handling the device when it is being installed on the PCB. The ESD circuits were not designed to protect the pins from system level ESD events after being installed on the PCB.  Your system design must protect the device pins from any Electrical Over-Stress (EOS) event after it has been installed on the PCB.  Connecting unterminated signal traces to these pins would not be a good design practice since there is nothing to limit the voltage potential of these pins.

Is there a recommendation for AM62A3 device pin configuration connected to unterminated traces?

These questions have dependencies on your system design.

We are not able to make any specific recommendation because we do not know your intentions for the unterminated traces. You need to make sure the potential applied to AM62Ax pins remain within the limits defined by the device datasheet.

For example, the potential applied to a device pin must never exceed the Steady-state max voltage level defined in the Absolute Maximum Ratings table and the potential applied to any enabled input buffer must remain below the VILSS or above the VIHSS levels defined for that IO type unless the signal is changing logic levels while not violating the minimum slew rate limit for that IO type.

You will need to determine the potential that can be produced when energy from electrical noise or crosstalk couples into these unterminated traces and apply the appropriate termination to ensure the above. The answer to this question will be specific to you PCB design and the operating environment of your system.

Specification of output voltage of LVCMOS

The customer is trying to use the LVCMOS output pin with 1.8VMODE, but the maximum vol value is 0.45V (IOL = 3mA), which is a high specified value, and the design does not work if the electrical characteristics are interpreted as it is.

Assuming that vol is specified by the on resistance of the NMOS of LVCMOS, is it correct to assume that if an external PD is prepared, the IOL is 0 mA, so the actual vol is 0 V (because the voltage drop at the on resistance of the NMOS does not occur)?

The max limit defined for VOL is valid as long as the IOL is less than 3mA, and the min limit defined for VIH is valid as long as the IOH is less than 3mA.

The datasheet is saying the output buffer is able to sink current up to the min IOL current of 3mA and the low-level output voltage will remain less than the max value of 0.45V defined for VOL, and the output buffer is able to source current up to the min IOH current of 3mA and the high-level output voltage will remain greater than the min value of (VDD - 0.45V) defined for VOH.

 https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1534012/am6422-connecting-unused-processor-ios-or-power-pins-or-nc-pins 

AM6422: Connecting unused processor IOs or power pins or NC pins

How does a circuit act as a LVCMOS buffer?

AM62P treatment on unused pins

Most LVCMOS pins will be turned off by default, so these pins can be left unconnected if software never enables the input buffer associated with a pin. A pin which has its input buffer enabled must never be allowed to float to a mid-supply voltage greater than VILSS and less than VIHSS. Input buffers may be damaged if it spends too much in the mid-supply region. 

Voltage on an unconnected AM62Dx pin is possible. The voltage observed on the pin is the result of leakage paths in the IO buffer, where the leakage can be as much as 10uA to either VSS or VDDSHV. This is normal as long as the leakage is not greater than 10uA. The resulting mid-supply voltage is not a problem for the AM62Dx device as long as the receiver (input buffer) in the IO buffer remains off. However, the pin must be driven or pulled to a valid logic level anytime the receiver is turned on. Never allow the input of an enabled input buffer in the AM62Dx device to float.

Note: We recommend external pulls to be used on any signal that connects AM62Dx to the input of another device. The external pull is needed to hold the signal in a valid logic state until software turns on the associated AM62Dx IO buffer such that it drives the signal to a valid logic state.

About VILSS and VIHSS

The VIL and VIH parameters are the traditional DC logic level thresholds, where the logic state will be low when the applied voltage less than or equal to VIL, high when greater than or equal to VIH, and undefined when greater then VIL and less than VIH.

The VIL and VIH parameters are the traditional DC logic level thresholds, where the logic state will be low when the applied voltage less than or equal to VIL, high when greater than or equal to VIH, and undefined when greater then VIL and less than VIH.

The VILSS and VIHSS parameters are associated with device reliability, where any steady-state potential needs to remain below VILSS or above VIHSS to minimize the input buffers shoot-through current. The input buffer has a limited amount of time it can spend in the voltage region between VILSS and VIHSS without long-term reliability concerns. This is why the Electrical Characteristics tables define a minimum slew rate parameter that constrains the amount of time an input is allowed to be in this region. The amount of time a signal can be within this region is a function of toggle frequency, with a maximum upper bound of 1000ns for rise/fall times.

The VILSS and VIHSS parameters are associated with device reliability, where any steady-state potential needs to remain below VILSS or above VIHSS to minimize the input buffers shoot-through current. The input buffer has a limited amount of time it can spend in the voltage region between VILSS and VIHSS without long-term reliability concerns. This is why the Electrical Characteristics tables define a minimum slew rate parameter that constrains the amount of time an input is allowed to be in this region. The amount of time a signal can be within this region is a function of toggle frequency, with a maximum upper bound of 1000ns for rise/fall times.

LVCMOS IO configuration 

Example: OSPI0_LBCLKO

Most of the AM62Px IOs default to mux mode 7, which selects the GPIO signal function. The IO cells associated with these pins default to an off state, where the input buffer is turned off, the output buffer is turned off, and the internal pulls are turned off. It is possible to allow these pins to float as long as software never turns on the input buffer with the RXACTIVE bit in the respective PADCONFIG register. You should never allow any of these pins to float to a mid-supply level between VILSS and VIHSS while the input buffer is enabled because exposure to this condition could damage the input buffer.  We limit the time allowed in this mid-supply region when the input is enabled by defining a minimum input slew rate for each buffer type in the Electrical Characteristics section of the datasheet.

The IO associated with the OSPI0_LBCLKO pin is internally connected to the GPIO module when MUXMODE is 7. However, the IO cell will be turned off by default and will remain off until software turns it on.

Software can enable the input buffer, enable the output buffer, or enable the internal pulls independently via the PADCONFIG register. So, the state of the pin depends on how software configures the PADCONFIG register. Once the PADCONFIG register is configured, it will depend on how the GPIO0 module is configured when MUXMODE = 7, or how the UART5 module is configured when MUXMODE = 5, or how the OSPI0 module is configured when MUXMODE = 1.

Slew Rate

The min slew rate defined in the electrical characteristics defines the max transition time allowed for the signal sourcing the input buffer to prevent any long-term reliability concern which can occur if the applied voltage spends too much time in the mid -supply region defined by VILSS and VIHSS.

There can be long-term reliability issues associate with the input buffer if the applied signal spends too much time in the voltage region between VIHSS and VILSS. The maximum transition time allowed is 1000ns. I recommend driving the reset input with a push-pull buffer that produces a signal transition rate that is faster than 5ns to eliminate the risk of noise coupling into the signal as it transitions through the input buffer switching threshold.

We basically need to limit the amount of time the input buffer is exposed to a mid-supply potential. The concern is related to electromigration in the input buffer caused by shoot-through current that flows from VDD through the input buffer to VSS as the signal transitions through the mid-supply region. The slew rate limits ensure the device is not exposed to this condition for too long over the life of the product.

The risk associated with violating the limit is the possibility of the input buffer failing before the device POH limit.

 There is no maximum input slew rate for the "LVCMOS" buffer when operating at either voltage, so you do not need an RC to slow the signal slew rate. You only need to be concerned with the minimum input slew rate limits defined in the "LVCMOS" Electrical Characteristics table.

The slew rates defined in the Electrical Characteristic sections are a function of long-term reliability, where these parameter values limit the amount of time the input buffer is exposed to a mid-supply potential over the lifetime of the device.  The input slew rates defined in the respective Timing Conditions table are a function of peripheral timing closure, where we only define values required to support the max operating frequency.  It is not possible for TI to define input slew rate values for every possible operating frequency, so we expect the input slew rates to compliant to the limits defined in the Timing Conditions Table for all operating frequencies.  

 The input slew rate limits associated with the GPIO signal function will be relaxed in the next revision of the AM62x datasheet.  The new values are shown in the snapshot inserted below.

I suspect some of their issue is potentially measurement error being introduced by not measuring the input slew rate at the far end of the signal trace.  An LVCMOS signal will have a mid-supply step that occurs any point along the signal trace other than the far end.  This step will add time to a slew rate measurement when measured at any point along the signal path other than the far end.  For example, measuring the slew rate on a signal by placing the probe one inch from the far end of the signal trace will add about 330pf of error to your slew rate measurement.  We need to make sure the slew rate measurements are being taken at the far end of the signal trace, or make adjustments to the measured data to account for the error introduced by the mid-line signal distortion.

Rise/Fall time measurements will typically have an additional 330ps of rise/fall time per inch from where the probe is placed relative to the far end of the signal trace.  You may be able to subtract this additional rise/fall time from your measurements if you know where the probe was place relative to the far end of the signal trace.  If so, this will allow you to determine the actual slew rate that occurs at the far end of the signal trace.

I have inserted a snapshot that shows three signal waveforms, where the one on the left represents the signal shape at the source, the one in the middle represents the signal shape at the middle of the PCB trace, and the one on the right represents the signal shape at the far end of the signal trace.  Note: The PCB trace shown in this snapshot has an AC characteristic impedance that is equal to the output buffer source impedance and a propagation delay of T.  The same mid-supply voltage step occurs when your PCB trace has a AC characteristic impedance of 50 ohms and the output buffer source impedance of about 50 ohms.

The duration of the mid-supply voltage step will be two times the PCB trace delay at the source.  This is how long it takes for the initial mid-supply transition to propagate to the far end of the PCB trace and reflect back to the source.  

 The duration of the mid-supply voltage step will be equal to the PCB trace delay at the middle of the PCB trace.

 There is no mid-supply voltage step at far end of the signal trace.

 This mid-supply voltage step stretches the rise/fall time measured by the duration of the mid-supply step, which is a function of where the probe is placed along the PCB trace.  The duration of the mid-supply step measured by probing somewhere in the middle of the signal trace will be the time it takes for the signal to reach the far end of the signal trace after it passes the probe point plus the time it takes for the reflection to return from the far end of the signal trace back to the probe point.  The typical propagation delay of most PCB signal traces is about 167ps/inch.  This is why my 1 inch example mention in the previous reply would have a mid-supply step duration of about two times 167ps.  For this example, you would need to subtract about 334ps from the measured rise/fall time to get a better understanding of what the actual slew rate would be at the far end of the PCB trace.

AM623: Rise/Fall Time Requirement of MMC_CLK

We define timing requirements for AM62x inputs and define timing characteristics for AM62x outputs.

We do not define any rise/fall switching characteristics associated with AM62x outputs because these characteristics are very dependent on the specific system implementation. The system designer must use the IBIS model of each device connected to a signal and the PCB signal trace extractions in a simulation to determine the rise/fall time of any signal being sourced by AM62x.

Connecting capacitor (load) at the LVCMOS IO output for EMI control

There is a Timing Conditions table at the beginning of each peripheral timing section in the datasheet, where the maximum capacitance is defined. Your system should be designed to be compliant to the max capacitance defined in the respective Timing Conditions table.

The max output load capacitive defined in the datasheet is the combination of everything connected to the pin.

Connecting a 100pf capacitor directly to the output buffer causes large peak current to flow through the AM64x power rails and output buffer to the capacitor. This large capacitive load applies more stress to the output buffer than expected and introduces larger than expected ground bounce which introduces noise into the entire AM64x device.

Inserting a series resistor before any discrete capacitor load will reduce the current that flows through the AM64x power rails and output buffer. However, the RC circuit would need to be placed near the AM64x device to be effective in reducing the signal slew rate which is what you are trying to do to reduce EMI.

EMI issues is a typically a system implementation issue and has many variables which influence the profile of radiated emissions. PCB layout issues are the mostly likely contributor. For example, a common contribution to EMI has been seen when customers route signals through board to board connectors or board to cable connectors without low loop inductance return ground paths which can cause signals to radiate noise. Is the SPI_CLK signal routed such that it has a low impedance return reference along the entire path of the signal?  For example, does the signal cross any split reference planes or does it transition from one reference plane to another reference plane without a nearby a stitching via or stitching capacitor?

Slew Rate control

The IO cells used in AM64x do not have slew rate control.

The IO cells were designed to include drive strength control, which effectively changes the source impedance of the output buffer.  Changing the impedance of the output buffer may have a small impact on the signal slew rate, but that is not the purpose of implementing drive strength control.  The primary purpose for including a way to change output buffer drive strength is to match the impedance of an output buffer to the impedance of a PCB signal trace.  This drive strength control function is used to eliminate signal distortion that is the result of reflections on the signal traces when the output buffer impedance doesn’t match the AC impedance of the signal trace.

 The drive strength control implemented in AM64x has been set to fixed values such that the output buffers source impedance matches a typical PCB trace impedance.  The Am64x LVCMOS IOs were timing closed with the default drive strength. Therefore, we do not recommend changing the drive strength since this could be introducing signal timing issues with the attached device.

 In summary, there is no way to internally control the slew rate of a GPIO output signal.  They could insert a low pass filter on the signal to reduce the slew rate.

Could you provide the rise/fall times and slew rates of drivers (IO cells) of MMC1 (SDIO) at 3V3 and 1V8 in different modes (specially default mode at <25MHz)?

We do not define output rise/fall times because these parameters depend on the actual system implementation. You will need to use the IBIS model for the respective AM64x pin and simulate the rise/fall times based on your actual PCB load.

Drive Strength Configuration

TI currently does not support configuring any other drive strength besides the nominal (default) value for SDIO and LVCMOS buffers, as the nominal value is the only configuration at which chip-level STA (Static Timing Analysis) is closed. The nominal value corresponds to a 40Ω for SDIO and 60Ω for LVCMOS. The IBIS model has been updated to contain only drive strengths where the timing is closed internally.
We do not currently support changing the drive strength.
The SOC was designed for proper operation when using the default drive strength.
Changing the drive strength may cause functional issues. Therefore, we currently do not support changing drive strengths.
The drive strength must remain in the default state since this is the only condition used during timing closure of the peripherals.

The latest IBIS model on TI.com should have the updated configurations. Ensure customer uses the update IBIS model on TI.com.

Will the drive strength information be included in the Datasheet?

This type of information is provided in the device IBIS file. We only provide these details in the IBIS model.

Customers that need electrical characteristics associated with IOs are typically doing simulations to validate their design. Therefore, we provide these details in the IBIS file to make it easy for our customers to import the data into their simulation environment. The IBIS files are created using an automated flow, where the information is taken directly form the design. This prevents data entry errors that may occur if we manually entered this information in the datasheet. We decided several years ago to stop including many of the IO electrical characteristics in the datasheet and only provide this information in the IBIS file.

The DRV_STR setting doesn't directly impact the DC mA capacity.  It does have an affect on the transition/edge of the signal

nRSTOUT for MCU_PORz Slew

Please keep in mind the AM62Ax device requires the MCU_PORz input to have a maximum rise/fall time of 1000ns. This may be difficult to achieve with a pull-up on a signal sourced from an open-drain output buffer. You may need to buffer the open-drain signal with a push-pull buffer that has hysteresis on its input to ensure the AM62Ax device never receives a short reset pulse that violates the minimum pulse duration defined in the "MCU_PORz Timing Requirements" table. For example, it may be possible for noise to couple on the slow rising open-drain signal just as it crosses the input buffer threshold which could cause a short glitch on the reset signal. Normal device operation could be compromised if this occurs.

See the "Input Slew Rate" parameter in the "Fail-Safe Reset (FS RESET) Electrical Characteristics" table.

The MCU_PORz input is the only input on the AM62x device that is fail-safe and 3.3v tolerant. Therefore, you can pull the MCU_PORz signal to 1.8V or 3.3V.

See the "Steady-state max voltage at all fail-safe IO pins" parameter for MCU_PORz in the "Absolute Maximum Ratings" table.

mid-supply potential to LVCMOS

Applying a mid-supply potential to any CMOS input buffer that is enabled will partially turn on both p-channel and n-channels in the input buffer. This causes shoot-through current to flow from the IO supply to ground. This shoot-through current could damage the input buffer if the condition remains for extended periods of time. Therefore, it is important for the system design to turn off any conflicting internal pulls as soon as possible.

Connecting Open drain output together 

 https://e2e.ti.com/support/logic-group/logic/f/logic-forum/865215/faq-with-open-drain-outputs-can-i-use-them-to-shift-a-logic-voltage-level-connect-the-outputs-directly-together-force-a-voltage-node-to-zero 

With an open-drain output, there is no danger of one output being HIGH and another being LOW since all outputs are either LOW or Hi-Z. In the above image we show how three open-drain buffers can be combined to produce a 3-input AND gate function. It is important to note that the output signal has the same limitation as the previous use-case: the signal can either be fast or low power, but not both.

Configuring GPIO as open drain outputs

It depends on the IO cell associated with the pin being used for the GPIO function in question. Look in the Buffer Type column of the Pin Attributes table to determine the IO cell implemented on the pin in question. A limited number of pins implement I2C open-drain fail-safe (I2C OD FS) IOs. These IOs only have open-drain output buffers, so you do not need to do anything to configure these IOs to operate as open-drain outputs. Most of the other pins that can be used as a GPIO implement LVCMOS IOs, which have push-pull output buffers. If you select one of these pins for your GPIO, they can be configured to operate as open-drain outputs by configuring the GPIO module to source a constant low output and toggle the output enable. The output buffer will drive low when enabled and will be high impedance when disabled.

Note: The (I2C OD FS) are the only IOs which are fail-safe. The other IOs do not allow any potential greater than (VDD + 0.3V) to be applied.  This means you can not source any potential to these pins when power is off. So make all attached devices with can source a potential to these IOs are powered from the same power supply that is sourcing the respective IO power rail. This eliminates any risk of this occurring.  

Regards,

Sreenivasa

Hi Board Designers, 

Refer below FAQs

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1443807/faq-am6442-how-does-lvcmos-buffer-behavior

Question to Absolute maximum ratings

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1490743/am2434-question-to-absolute-maximum-ratings/5730902

My customer is asking what is the reason the maximum voltage at IO pin is IO supply voltage+0.3V.
Is this to prevent an internal ESD diode from turning on?
If so, what is a problem with the internal ESD diode turning on?

Yes, the ESD protection circuits will turn on if the input is greater than IO supply voltage+0.3V.

We do not allow injection current through the ESD protection circuits because they were only designed to protect the device from short-duration ESD events that occur during device handling and PCB assembly. The ESD protection circuits are not designed for steady-state DC current or provide any system-level ESD protection once the device has been installed on a PCB.

peaves said: We do not allow injection current through the ESD protection circuits because they were only designed to protect the device from short-duration ESD events that occur during device handling and PCB assembly.
Do you have specific number for "short-duration"? 50msec duration would damage the device?

We do not allow any injection current from an IO voltage potential greater than IO supply voltage+0.3V, for any period of time.

My comment about short-duration was simply a reference to the typical ESD event profile that falls within the limits defined by the ESD standards listed in the ESD Rating table of the datasheet. As mentioned before, the ESD circuits were only designed to protect the device from ESD events similar to what would be introduced by a Human Body Model to account for device handling and a Charged Device Model to account for PCB assembly equipment. The ESD circuits were not designed to protect the device from system-level ESD events that occur after being installed on a PCB. However, the ESD circuits are still connected to the IOs. So, we must ensure the circuits are not damaged from unexpected injection current.

Residual Voltage / Injection current

The IOs associated with the AM62Px device are not fail-safe. This means no external circuit can source any potential greater than the potential applied to the respective IO power rail. See the "Steady-state max voltage at all other IO pins" parameter in the Absolute Maximum Ratings table in the datasheet, where the potential applied to a pin is limited to minimum of "-0.3V" and a maximum of "IO supply voltage + 0.3V".

The IO power rails of attached devices need to always have the same potential applied to prevent current injection into an IO that has a potential applied greater than the limits defined in the datasheet. For example, if one device is turned on the other device must be turned on, if one device is turned off the other device must be turned off. Their IO supplies also need to track as the power source ramps up or down. The best way to ensure this condition, is to power the IOs associated with both devices from the same power source.

The ESD protection circuits associated with an IO will turn on if the potential applied is greater than IO supply voltage+0.3V. This condition will inject current from the external voltage source through the ESD circuits to the IO power rail. We do not allow injection current through the ESD protection circuits because they were only designed to protect the device from short-duration ESD events similar to what would be introduced by a Human Body Model to account for device handling and a Charged Device Model to account for PCB assembly equipment. The ESD protection circuits are not designed for steady-state DC current. They also were not designed to provide any system-level ESD protection once the device has been installed on a PCB.

Regards,

Sreenivasa

Hi Board Designers, 

Refer below

1) What's the max current input and output for SDIO DATA/CMD line? (2) What's mean for "input leakage current"?

(3) Could we "remove" external PU resistor for SDIO communication? (connect device is WiFi module, not eMMC or SD)
Because of PCBA space limitation. we try to remove external PU resistor, and we found SDIO level become 1.2V. Does it have side effect?

(4) Does SDIO interface support internal PU resistor by register setting? Could we use internal SDIO PU resistor to replace external resistor?

We define output current as IOL and IOH parameters, which is the minimum Low Level Output Current and High Level Output Current for which the device is able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current available to a system implementation which needs to maintain the specified VOL and VOH values for attached components. You will need to use the AM62x IBIS models in a simulation to determine VOL or VOH levels for a specific current.

We plan to include the following input leakage note in the next revision of the datasheet. Hopefully, it helps explain what this parameter defines.
This parameter defines leakage current when the terminal is operating as an input, undriven output, or both input and undriven output, without internal pulls enabled.

Most of the AM62x pins will be turned off after power-up. This means the input buffer is disabled, the output buffer is disabled, and the internal pulls are disabled. Please reference the Pin Attributes table in the datasheet to see the initial power-up state of each pin. You may need to have external pull resistors on any signals that connect to inputs of attached devices to prevent them from floating until software configures the associated IO cell.
You can use the AM62x internal pull resistors if an external resistor is not required to hold inputs to a valid state while waiting for software to configure the internal resistors.

one question, Do we have minimum Low Level input current and High Level input Current for SDIO? Base on "7.8.5 SDIO Electrical Characteristics", I do not see related parameter. So I am not sure this is a right question.

The max input leakage is defined for the two worst-case conditions, which occurs when the voltage applied to the input is 0V or the IO power rail potential. See the test conditions associated with the input leakage current parameter. We do not define input leakage at VIL or VIH, but the leakage current will decrease as the voltage potential applied to the input moves away from either of the two test conditions.

Regards,

Sreenivasa

Hi Board Designers, 

Refer below

Driving an LED - Source or Sink using processor LVCMOS IO 

 We do not expect our outputs to be used to direct drive LEDs.  The output currents defined in the datasheet should not be used as limits for steady-state currents.  The datasheet output current limits are only expected when charging or discharging signal capacitance to transition a signal from low to high or from high to low.  Once the signal reaches a valid logic state, the steady-state current is expected to be much lower.  The outputs can tolerate some steady-state current as required to over-drive typical pull resistors, but we do not expect large stead-state currents like what is needed to drive an LED.

When driving an LED for a short duration using processor LVCMOS IO, the IO is recommended to be configured as output to be able to sink or source current

The LED supply is recommended to be powered from the same IO supply for IO supply group power source referenced by the LVCMOS IO.

The input impedance of the LVCMOS input is high. The current drawn is the leakage.

Recommendation is for customer to use a transistor or FET logic to drive the LED at 5V and control using the processor IO.

The recommendation is to use a transistor or FET logic to drive the LED at 5V and control using the processor IO.

Due to a design issue with the board, there is a period of time during which the high-level output pin of AM2431 is shorted to a low-level output pin of another IC.

Could you please provide the maximum allowable current for LVCMOS operating at 3.3V?

We do not expect our output buffers to ever be used in an application that requires it to source any significant DC steady-state current.  We only expect the output buffer to source significant current when the signal is changing logic states.  The only DC steady-state current expected is associated with holding the signal at the opposite logic state of a weak pull resistor.

The peak current that occurs during this contention condition could be very high and may damage one or both devices.  They definitely should not allow the source impedance of the two output buffers to be what limits the current.  They need to resolve the conflict, or at insert a current limiting resistor between the two devices.  However, this current liming resistor may have a significant impact on signal quality if the signal needs to operate with a fast toggle rate.

We do not define a max DC current.  We only define an output current operating condition, where we know the output buffer is able to drive a signal below the VOL limit or above the VOH limit.  They should be okay if they limit the current to less than 3mA, which is the output current operating condition that is being used for the VOH

Regards,

Sreenivasa

Hi Board Designers, 

Refer below input on the LVCMOS slew

What is the applicable range of the throughput rate spec? It is from 10% to 90%

Regards,

Sreenivasa

Hi Board Designers, 

Refer below input on connecting unused IOs

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1452150/am62a7-q1-unused-ball-l17-gpmc0_oen_ren/5570179

in case the ball L17 GPMC0_OEN_REN is not used, can the ball let open or a pull-up/down is recommended?

The ball can be left unconnected (no signal trace connected to the ball) as long as your system software never turns on the input buffer via the RX enable bit of the associated padconfig register.

Any IO with its input buffer (RX) turned off is allowed to float without damaging the device. However, any IO with its input buffer (RX) turned on shall never be allowed to float to any potential between VILSS and VIHSS. The input buffer can enter a high-current state which could damage the IO cell if allowed to float between these levels.

Refer pin connectivity section for the below notes 

Regards,

Sreenivasa

Hi Board Designers, 

AM625: Disturbance on OSPI CLK connected to SPI NOR

I personally think it is a mistake providing multiple chip select pins on this peripheral. It is misleading and makes someone think they can connect multiple devices, when this implementation is very problematic. 

The problem with connecting multiple devices is related to your observation on the clock. You see this distortion on the source end of the signal trace because the output buffer has about the same source impedance as the signal trace. When the signal changes from low to high or high to low, the voltage applied to the signal is divided by the ratio of output buffer source impedance and the signal trace impedance. It is basically a voltage divider that results in a mid-supply voltage being applied to the signal. This mid-supply voltage propagates down the signal trace until it encounters a high-impedance or open-circuit, where the mismatch in impedance results in an in-phase reflection that causes the voltage at the far end to make a continuous transition from VDD to VSS or VSS to VDD. This reflection returns back to the source, where the voltage at the source will not continue to VDD or VSS until this reflection has returned. The length of the mid-supply step function will be equal to two times the propagation time of the clock signal trace. The step function gets shorter as you get closer to the end of the signal trace, but not completely gone until the very end.

A device connected anywhere other than the far end of the signal trace will observe the same step function on the clock signal. Connecting a device clock input anywhere in the middle of a clock signal trace is a very bad design practice because there is a good chance the output of the clock input buffer of this device will generate internal clock glitches when this mid-supply voltage pauses near the switching threshold of the input buffer. You cannot split the signal trace into two paths without creating impedance discontinuities which also causes signal distortion. Inserting buffers will resolve the impedance mismatch issue but inserts delay in the clock path, which may cause a timing violation because the peripheral was timing closed assuming a direct connection without any buffer delays.

Connecting your NOR memory device to the middle of the clock signal was a mistake. You must resolve this issue by disconnecting any signal trace that extends beyond the attached device to prevent any internal clock glitch issues.

Most of the AM62x pins power-up turned off, so you need include external pull resistors to hold any attached device inputs in a valid logic state until the IOs and associated peripheral module has been initialized by software. You should never allow CMOS inputs to float. this is especially true for the AM62x inputs. All AM62x inputs which have been enabled must be held in a valid logic state that is above the VIHSS or VILSS as defined in the respective electrical characteristics section of the datasheet. The AM62x device could be damaged if your design allows any enabled inputs to float to mid-supply voltages for an accumulated period of time over the life of the product.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1164397/am625-disturance-on-ospi-clk-connected-to-spi-nor/4388721

Regards,

Sreenivasa

Hi Board Designers, 

About SPI signal series resistor

A value of 33 ohms may actually be better than 22 ohms. The most important thing is placing the resistor close to the AM64x device to minimize the signal trace length that connect the series resistor to the AM64x pin. This is required because the SPI clock pin is operating as input and output at the same time, where the internal data capture clock is looped back in the AM64x IO buffer. This is done to help with timing closure of SPI by inserted an equivalent delay in the looped back clock as the returned data path sees with the delay inserted by the clock output buffer and data input buffer. However, this approach impacts signal integrity at the looped back clock pin.

The help explain this issue, lets assume the output impedance is equal to the trace impedance. In this case the source end of the signal trace will only transition to mid-supply initially when the clock toggles. The signal will propagate the far end of the signal trace where it encounters a high-impedance mismatch which causes an equivalent amplitude reflection that returns to the source. For the time it take for the signal to propagate down and back, the voltage applied to the source pin will remain mid-supply. This is very likely to create glitches on the clock being looped back into the SPI controller. These glitches may over-clock the state machine and cause unpredictable operation. Adding a series resistor allows the voltage to step beyond the switching threshold, which prevents glitches. A 33 ohm will allow the voltage to step further away from the switching threshold than the 22 ohm. Increasing the resistor too much will compromise clock transition time, which may impact performance. I would avoid going higher than 33 ohms unless you observe an issue where the step function on the signal is causing problems.

The signal trace that connects between the pin and resistor will create a similar step and this is unavoidable. However, the step will be filtered by the input buffer if short. This is why it is important to keep this trace short.

Hopefully, this explains why we require these resistors and why they need to be close to the source pin 

Regards,

Sreenivasa

Hi Board Designers, 

About series resistor on clock input

e2e.ti.com/.../3851264

I did not see any de-coupling capacitors between on the AM335x VDDSHV4 power pin after low pass filter L704. Were these accidently omitted in the snapshots provided? If not, each power pin needs local de-coupling capacitors after their respective low pass filters.

I’m concern with the SD Card ground connections. Hopefully the SD Card VSS1 and VSS2 pins are connected directly to the same ground as the AM335x device. I assume the other grounds shown for the SD Card are simply the metal chassis ground and they are not part of the SD Card signal and power ground connections.

They should not be using a zero ohm resistor for R514. This should be a 22 - 50 ohm resistor. The MMC/SD host controller in AM335x loops the clock back at the pin to improve timing margin for the internal circuits. However, there is a negative side effect of implementing clock loopback on a pin. The clock signal will be distorted on the source end of a signal trace and a series resistor of 22 - 50 ohms is required to modify the signal distortion such that is does not create a glitch on the looped back clock signal.

I will explain what happens. The clock output buffer inside AM335x has a source impedance of about 30- 50 ohms and a typical PCB signal trace has a characteristic impedance in the range of 40 - 60 ohms. When the output buffer toggles the signal from low to high or high to low, the voltage of the pin which sits between the output buffer and the PCB signal trace will not transition to the expected voltage immediately. This is because the output buffer impedance and trace impedance create voltage divider that causes the pin to step to a mid-supply voltage for a short time. This step will last as long as it takes for the clock signal to travel down the PCB signal trace to the SD Card, where it encounters a high impedance load that creates a reflection that allow the voltage  to increase to VDD or VSS. The amplitude of the mid-supply voltage step may be near the AM335x clock buffer input switching threshold, which allows noise to create a glitch on the AM335x internal clock. The series resistor raises the impedance of the PCB portion of the voltage divider such that the voltage at the pin steps above or below the switching threshold.

I suspect this is what is causing the instability and the reduced clock amplitude is contributing to the issue.

I explained the purpose of the series resistor. A series termination resistor in the range of 22 - 50 ohms should be located as close as possible to the AM335x MMC0_CLK pin to shift the clock distortion away from the looped back clock input buffer switching threshold. 

However, how do we choose the best value for series resistor? I haven't observed the difference from waveform when changing R514 from 0 to 22 Ohm.

What you observe on this signal depends on where you connected the probe, the bandwidth of your probe/scope, and quality of your scope probe ground. 

You will need a very high bandwidth probe and scope to observe short over-shoot, under-shoot, and non-monotonic events on the signal. I recommend using a low capacitance FET probe with a very-very short low loop inductance ground.

You will see a mid-supply step on the signal when probing near the source. This occurs because the output impedance of the MMC0_CLK output buffer, series termination resistor, and characteristic impedance of the PCB signal trace creates a voltage divider. The voltage divider output is applied to the source end of the PCB signal trace. This voltage propagates down the trace to the far end where it encounters a high impedance load which causes a in-phase reflection that returns to the source. Therefore, the voltage transition observed on the far end will be a continuous transition between VSS and VDD. The is not the case for the source end, as it steps to a mid-supply determined by the voltage divider values and the transition only continues to VDD or VSS once the reflection returns from the far end. You need to select a series resistor value that allows the MMC0_CLK pin to step through the voltage of (VDDSHV4 / 2) without pause. I suggest the step observed on the MMC0_CLK pin should be at least 200mv above (VDDSHV4 / 2) on the rising edge and at least 200mv below (VDDSHV4 / 2) on the falling edge.

Regards,

Sreenivasa

Hi Board Designers, 

Refer below for information related to PMIC_LPM_EN0

AUDIO-AM62D-EVM: PMIC_LPM_EN0(D12) pin is getting Reset when it is Pull Down (Direction is out)

1.what is the function of PMIC_LPM_EN0(D12) pin?

2. What is the use case of this pin?

3.What is the default pin configuration of this?
Note: When this pin configured as Pull Down (Direction is out), system getting reset, when this pin configured as Pull Up (Direction is out), system is working fine  

Pin D12 defaults to the PMIC_LPM_EN0 signal function. This signal is used to control the PMIC.
When using Partial IO low power mode, the signal is used to turn off the switched power rails when software configures the Partial IO logic to enter Partial IO low power mode and turns on the switched power rails back on when the always powered Partial IO logic detects a wakeup event.
When using the PMIC_LPM_EN0 signal as described above, an external pull-up to the VDDSHV_CANUART power source is required. The pin will be high-Z during reset, which allows the pull-up to turn on the PMIC as soon as the always on VDDSHV_CANUART supply ramps up. The pin will be driven high once the device is released from reset (rising edge of MCU_PORz). It will remain high until the device has been put into CANUART mode and told to enter low power, where it is driven low to turn off the PMIC. It will be driven high once again when the CANUART detects an external wakeup event. When not using Partial IO low power mode, the signal can be used to change the operating mode of the PMIC to a lower power configuration when software places the device in deep sleep mode. After the device has booted, software can configure pin D12 to function as MCU_GPIO_22 if the PMIC_LPM_EN0 signal function is not required.

Note: The explanation is applicable to AM62x, AM62A, AM62D-Q1 and AM62P family of processors.

Regards,

Sreenivasa

Hi Board Designers, 

Refer below for information related to unused SOC GPIOs

Regards,

Sreenivasa

Hi Board Designers, 

Additional references:

(+) [FAQ] AM62x, AM62Ax, AM62D-Q1, AM62L, AM62Px, AM64x, AM243x, Custom board hardware design – How to handle Used / Unused Pins / Peripherals and add pullup or pulldown? (e.g. GPIOs, SERDES, USB, CSI, MMC (eMMC, SD-card), CSI, OLDI, DSI, CAP_VDDSx, .....) - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hi Board Designers, 

Inputs regarding the specifications of the AM62P MCU_ERRORn (G6) pin:

Q1.
Section 6.3.3.3 of the TRM states:
"While in Power-On-Reset, the Error Pin is active (asserted low). SoC drives a Low via a weak internal pull-down."
Does this mean that during Power-On-Reset, the SoC does not actively drive the MCU_ERRORn pin low as a CMOS output, but instead pulls it low using a weak internal pull-down resistor?

Q2.
Is the internal pull-down resistor for MCU_ERRORn the one specified in the Data Sheet section 6.8.7 “LVCMOS Electrical Characteristics” as RPD: 15–30 kΩ?

Q3.
If we connect an external pull-down resistor to the MCU_ERRORn pin, is there a recommended resistance value?

A1. The IO cell associated with the MCU_ERRORn pin has its input and output buffers turned off, and its internal pull-down turned on while MCU_PORz is asserted. The input buffer and output buffers will be turned on, and the internal pull-down will remain turned on when MCU_PORz is de-asserted. The ESM will drive a high logic state shorty after MCU_PORz is de-asserted, and this state will remain until the ESM has been initialized and an error detected.

A2. Yes, the IO cell associated with pin G6 is the LVCMOS buffer type. You need to understand the internal pulls are not linear resistors. The pull resistance increases as the signal potential approaches the power rail that is pulling the signal. The datasheet values represent the range of pull resistance expected when the signal is pulled to the opposite power rail. We do not define the internal pull resistance for any other operating condition. You will need to use an external resistor if your application requires a linear pull resistor.

A3. The VOH and IOH parameter values represent a single data point that says the output buffer is able to source a voltage greater than VDD - 0.45 when a 3mA load is connected. The voltage is likely to be much higher than VDD - 0.45V with a lower current load. However, you will need to use the device IBIS model to determine the output voltage for any other load condition.

Note: The input buffer associated with this IO cell is enabled to allow the MCU_ERRORn signal to be looped back into the device through the IO cell, so you need to make sure the steady state potential applied to pin G6 is greater than VIHSS (0.85VDD) or less than VILSS (0.3VDD) to prevent any long-term reliability issues with the input buffer. You will need to consider the worst-case input leakage of the AM62Px IO cell (10uA), the min resistance of the internal pull-down (15k), the worst-case input leakage of all other devices connected to the MCU_ERRORn signal, as well as the load presented by the external resistor when trying to determine the output voltage when driven high.

Regards,

Sreenivasa

Hi Board Designers, 

Inputs regarding padconfig bit TX_DIS

Data sheet reference 

Pin attributes table 

BALL STATE DURING RESET RX/TX/PULL: State of the terminal while MCU_PORz is asserted, where RXdefines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of

internal pull resistors:

• RX (Input buffer)

– Off: The input buffer is disabled.

– On: The input buffer is enabled.

• TX (Output buffer)

– Off: The output buffer is disabled.

– Low: The output buffer is enabled and drives VOL.

• PULL (Internal pull resistors)

– Off: Internal pull resistors are turned off.

– Up: Internal pull-up resistor is turned on.

– Down: Internal pull-down resistor is turned on.

 NA: Not Applicable.

• An empty box means Not Applicable.

The PADCONF regs can independently enable or disable the input path (RX_ENABLE) and the output path (TX_DIS). This might conceptually be done to minimize power consumption. Or as another example, you may want to "guarantee" that a particular GPIO is limited to functioning as an input (RX_ENABLE=1) and should never be allowed to "accidentally" drive an output (TX_DIS=1) (though "accidentally" having GPIO to drive an output can only happen in the case of a software bug)

Once those two buffers are enabled, then the MUXMODE dictates which IP can dynamically control the corresponding IO.

If for example you're in GPIO mux mode ...

At any given instant the output path can be high-z or actively driven. If you tell the pin to act as an output, then the GPIO module drives the "output_enable" of the IO buffer (making it "not" high-z) and the output value from the GPIO module is driven on the output *and* reflected back on the input path if the RX_ENABLE is enabled. And the GPIO IN value will reflect the state of the output value.

If the RX_ENABLE is "disabled" then you would not see the GP In reflecting the GP Out.

Similarly, if TX_DIS=1 then the GPIO "output enable" is gated off and regardless of what is set in GP OUT will not reflect on the output pad.

Additional inputs i received from our device expert for TX_DIS.

This bit was added because the pin mux logic is not glitch free when changing modes. For example, the pin mux logic may connect the output of any of the signal function to the IO cell for a very short duration when switching from one mode to another. This may cause the attached signal to glitch to an unknown logic state or multiple unknown logic states before settling to the logic state of the newly selected signal function. This glitch may be undesirable for some applications. If that is the case, the TX_DIS bit provides a way for the application software to force the output buffer off before making the mode change. Note: The attached device may require an external pull or the internal pull to be turned on to hold the signal in a known state while the TX_DIS bit is set. The input buffer associated with the IO on our device will have a similar requirement if the input buffer is enabled with the RXACTIVE bit. An alternative for protecting our IO would be to turn off the associated input buffer before turning off the output buffer.

Once the mode has been changed, the TX_DIS bit can be returned to its functional state. The RXACTIVE could be turned back on if it had to be turned off. Then software can begin using the new signal function.

In some cases the application may not care if the signal glitches. If so, this process of disabling the output buffer during a mode change may not be necessary.

Regards,

Sreenivasa

Hi Board Designers, 

Inputs regarding padconfig bits

The lock bit is used with the safety software.

Hi Board Designers, 

General design notes related to IOs

Hi Board Designers, 

Queries related to GPIO grouping and supply connection:

Refer 6.3 Signal Descriptions for IO related to the DPI 

Table 6-9. DSS0 Signal Descriptions

The table lists all the signals used for DPI interface 

A number of LVCMOS IOs  are grouped together and a common supply for the group IO supply for IO group VDDSHVx is the supply referenced for the whole group.

Each of the IO supply group can be sourced by a fixed 1.8V or 3.3V supply.

Refer 6.2 Pin Attributes section of the data sheet for the GPIO information related to IO supply for IO group. 

The DPI signals (VOUT0_) are referenced to IO supply for IO group VDDSHV3

The IO buffer type is LVCMOS 

Refer below section for the specs

7.8.6 LVCMOS Electrical Characteristics

The IO levels is recommended to be above VIHSS or below VILSS.

The links to the data sheet and other collaterals are provided in the below FAQ

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1183910/faq-am625-custom-board-hardware-design-collaterals-to-get-started

Regards,

Sreenivasa

Hi Board Designers, 

Refer below for GPIO timing and slew rate 

7.11 Timing and Switching Characteristics

(+) [FAQ] AM623: MMC0 HS200 slew rate - Processors forum - Processors - TI E2E support forums

1) We only define Input slew rate for modes which have specific or fixed input timing requirements. The clock output to data capture time relationship is not fixed for the HS200 read data path since this mode requires data training. The data training algorithm used a known data pattern to select a data capture time that is centered in the data valid window. There is no specific input slew requirement since tuning searches across an entire bit time to find the center of the data valid window. However, the width of the data valid window is a function of input slew. The signal transition needs to be fast enough to provide a reasonable data valid window for the data training algorithm.

2) It is very important to limit the amount of time the applied signal spends within the voltage region between VIHSS and VILSS. The minimum input slew rate limits are required to ensure long-term reliability of the input buffer. 

The minimum slew of 1.8E+6V/s (1000ns when operating at 1.8V) is not a function of toggle frequency and it represents the slowest signal that can be applied to the AM62x input buffer. The minimum slew of 18fV/s (0.5ns when operating at 1.8V with a 200MHz toggle) is a function of toggle frequency and represents the minimum slew rate allowed for a specific operating frequency. The limit of 18fV/s is the more restrictive of the two limits, so this is the requirement to ensure long-term device reliability. In some cases, a specific peripheral may have a more restrictive requirement to ensure timing. 

 See Note 5 associated with the Input Slew Rate parameter, SR_I. The note defines which value applies by saying "Select the MIN parameter which results in the largest value".

The non-frequency dependent limit of 1.8E+6V/s becomes the larger value when the signal toggle rate is less than 100kHz. 

The frequency dependent limit of 18fV/s becomes the larger value when the signal toggle rates is greater than 100kHz.

The slew rate has frequency dependency.

1,8V mode

3.3V mode

A max slew of 1000ns is recommended when the signals toggle rate is not high (non-frequency dependent limit)

We basically need to limit the amount of time the input buffer is exposed to a mid-supply potential. The concern is related to the effect on reliable operation of the input buffer caused by shoot-through current that flows from VDD through the input buffer to VSS as the signal transitions through the mid-supply region. The slew rate limits ensure the device is not exposed to this condition for too long over the life of the board.

The risk associated with violating the limit is the possibility of the input buffer failing before the device POH limit.

We only care about the signal slew rate that is applied to an enabled AM62x input buffer.

The slew rate is not a concern for CLK signal as long as they turn off the associated input buffer with the respective RXACTIVE bit. This will not be possible for the IOs associated with the DAT/CMD signals since they are bidirectional. The external series resistor should provide some isolation from the load when AM62x is driving DAT/CMD, which should allow the signal to have a faster slew rate at the AM62x pin. We are only concerned with the signal slew rate on the AM62x pin since that is what is sourcing the AM62x input buffer. The external series resistor should not have a big impact on the signal slew rate at the AM62x pin when the attached device is driving DAT/CMD.

They need to be measuring the signal slew rate of the AM62x pin. Where are they measuring the signal slew rate?

The eMMC clock in AM62x is not looped back for retiming. AM335x did not have internal delay lines that could be used to optimize timing, so the clock was looped back at the pad to help compensate for the some of the delay inserted in the roundtrip time associated with read operations. It would not be possible to close timing for the faster data transfer rates supported in AM62x without having the internal delay lines. You do not need to loopback the clock once you have internal delay lines to compensate for external delays.

When you say they are measuring slew rate close to AM62x, are they probing on the actual device pin.  If not, the measured slew rate will not be the same that is seen by the AM62x input buffer. For example, the measured slew rate will have a 100ps mid-supply step include in the slew rate measurement if they probe the signal 0.3 inches from the AM62x pin. The mid-supply step gets shorter as you probe closer to the AM62x pin and gets longer as you probe further from the AM62x pin. The slew rate measurement is only accurate when probing the signal at the AM62x pin.

You mention competitor devices do not have similar slew rate requirements. This may be the case if these devices were implemented in a less-advanced process node, where the circuit geometries are larger. It may also be possible that competitors do not understand the risk associated with an input speeding too much time in the mid-supply region.

The mid-supply step will be equal to 2 times the PCB trace delay at the output buffer. The mid-supply step will be equal to zero at the input buffer connected to the far end of the PCB signal trace. The mid-supply step decreases from 2 times the PCB trace delay to zero as you move the probe from the source to the end of the PCB signal trace. The mid-supply step will persist for the time it takes the signal to propagate past the probe to the end of the PCB trace and return back to the probe. The average propagation velocity of a PCB signal trace is about 167ps per inch. In my previous example, probing 0.3 inches from the AM62x pin, it would take the signal 0.3x167ps = 50ps to travel past the probe to the end of the PCB signal trace, then it would take another 0.3x167ps = 50ps for the signal to return to the probe. This step will add 100ps to any rise/fall measurement, which can have a significant impact on measured slew rate.

There are multiple reliability concerns. One is aging, that causes propagation delay through internal circuits to degrade over time. The CLK output path and the DAT/CMD output path may not age at the same rate, which means one signal can get slower over time relative to the other signal. The timing closure team may have already accounted for the delay degradation associated with the different toggle rates, where they based the timing impact on our recommended min input slew rate. Violating the recommendation could cause timing violations over time.

It is going to be very difficult to analyze all of the concerns with violating the recommended min input slew rate. The customer needs to make an effort to meet our input slew rate requirements.

About Input Slew Rate of LVCMOS in Datasheet 

The min slew rate defined in the electrical characteristics defines the max transition time allowed for the signal sourcing the input buffer to prevent any long-term reliability concern which can occur if the applied voltage spends too much time in the mid -supply region defined by VILSS and VIHSS. This parameter is unrelated to timing requirements.

The min slew rate defined in the GPIO timing section defines the max transition time allowed for the GPIO minimum pulse width Timing Requirements to be valid.

I have two questions.

1.LVCMOS in IBIS model has two types, LVCMOS_H and LVCMOS_V.
Is the slew rate spec same both types?

2.You say slew rate of the electrical characteristics is related to reliability.
Is it same to all peripherals?

We have two layouts for each IO cell design, The ones with a "_V" suffix are implemented along the vertical edges of the die and the ones with a "_H" suffix are implemented along the horizontal edges of the die. The slew rate requirements are the same for both.

The slew rate defined in the Electrical Characteristics tables are a function of the IO cell reliability. The slew rates defined in the various Timing Conditions tables are a function of peripheral timing.

Propagation delay through input buffers will increase as the slew rate decreases. The effect of slew rate must be considered for short duration timing parameters. However, the RST3 parameter is not one of those short duration timing parameters. The slew rate influence on the RST3 parameter is not significant.

(26) AM2432: IBIS Model - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

1. Looking into IBIS model(sprm730.ibs), there are two variations "LVCMOS_H" and "LVCMOS_V" for LVCMOS model. what's the difference between them?

The suffixes, _H and _V, refer to the orientation of the IO where _H is a horizontal orientation and _V is a vertical orientation. 

What are different LVCMOS_H with LVCMOS_V?

This references the layout orientation of the IO buffer on the die, H=Horizontal and V=Vertical.  

(+) [FAQ] TDA4VM-Q1: TDA4 Drive Strength Controls - Processors forum - Processors - TI E2E support forums

 https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1200155/faq-tda4vm-q1-tda4-drive-strength-controls 

        2. Looking into IBIS model(sprm730.ibs), it seems that there are six variations for LVCMOS_H (1.8V/3.3V x Nom/slow/Fast). Which one should I use for the simulation?

For the 1.8V vs 3.3V model, it depends on whether you plan to supply the IO supply VDDSHV<n> for IO group <n> with 1.8V or 3.3V. The datasheet lists each ball number's POWER. For example, The AM243x LaunchPad connects IO supply VDDSHV[0-4] to 3.3V supply and therefore all balls in the VDDSHV[0-4] power domain should be 3.3V models. 

Regards,

Sreenivasa

Hi Board Designers, 

Inputs related to GPIO ESD 

(+) [FAQ] AM2434: GPIO (pins) esd protection and maximum allowed voltages. - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Electrostatic discharge (ESD) protection circuits inside the processor are designed to protect the device from handling before being installed on a PCB assembly.

An external ESD protection is recommended to any of the processor IOs connected directly to an external connector or exposed to external inputs, because internal ESD protection circuit were not designed to handle the board level ESD requirements.

(+) Meaning : Min/Max of Clload (Output load capacitance) - Processors forum - Processors - TI E2E support forums

Meaning : Min/Max of Clload (Output load capacitance)

 I want to know the meaning of Min/Max Cload.   AM335x Datasheet said "GPMC Cload (Output load capacitance) is MIN 3pF, MAX 30pF" as follows.

 

 

 

 My understanding is that  when "the capacitor of between 3pF and 30pF" is attached on one of GPMC pins as the external load, AM335x can work under the datasheet timing.  Is it correct??  Please let me know. 

Yes, you are correct.  Timing parameters are verified with AM335x operating within the operating conditions defined in the Recommended Operating Conditions section of the data manual with a capacitive load in the range of 3 - 30 pF.

Regards,

Sreenivasa

Hi Board Designers, 

Inputs on GPIO propagation delay

(17) TDA4VM-Q1: Propagation delay for GPIO - Processors forum - Processors - TI E2E support forums

We are trying to measure/estimate the propagation delay from the TDA4 SoC to the Serializer (located on the camera). We have a GPIO connection between SoC and the Deserialzer. The latency between the time the application writes Logic High to be driven on one of the GPIO, to the time that the GPIO gets asserted is our area of interest

TDA4 --> Deserailizer -> GMSL Link --> Serializer --> Imager 

-------SoC---------------                               -------Camera--------

The latency between the time the application writes Logic High to be driven on one of the GPIO

If you are asking about the full latency from the time the application software sends a write request, that will likely vary depending on the initiator and software / system traffic, and thus not likely something we would be able to provide. 

regards,

Sreenivasa

Hi Board Designers, 

Inputs on LVCMOS input slew rate (MCU_PORz)

(+) [FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP: MCU_PORz input slew rate - Processors forum - Processors - TI E2E support forums

There can be long-term reliability issues associate with the input buffer if the applied signal spends too much time in the voltage region between VIHSS and VILSS. The maximum transition time allowed is 1000ns. I recommend driving the reset input with a push-pull buffer that produces a signal transition rate that is faster than 5ns to eliminate the risk of noise coupling into the signal as it transitions through the input buffer switching threshold.

A 22 pF glitch filter is recommended at the input of MCU_PORz

 another important point about the MCU_PORz input slew rate. It is very easy for noise to couple on slow rising signals such that it creates non-monotonic transitions. Your MCU_PORz reset source needs to be monotonic to prevent the chance of creating glitches on internal reset as it transitions through the input buffer switching threshold. A faster slew rate on the MCU_PORz will increase your system noise immunity. The min slew rate defined in the AM625 datasheet is acceptable to the AM625 device but may not be acceptable for your system noise immunity requirements.

Please keep in mind the AM62x device requires the MCU_PORz input to have a maximum rise/fall time of 1000ns. This may be difficult to achieve with a pull-up on a signal sourced from an open-drain output buffer. You may need to buffer the open-drain signal with a push-pull buffer that has hysteresis on its input to ensure the AM62x device never receives a short reset pulse that violates the minimum pulse duration defined in the "MCU_PORz Timing Requirements" table. For example, it may be possible for noise to couple on the slow rising open-drain signal just as it crosses the input buffer threshold which could cause a short glitch on the reset signal. Normal device operation could be compromised if this occurs.

See the "Input Slew Rate" parameter in the "Fail-Safe Reset (FS RESET) Electrical Characteristics" table.

The MCU_PORz input is the only input on the AM62x device that is fail-safe and 3.3v tolerant. Therefore, you can pull the MCU_PORz signal to 1.8V or 3.3V.

See the "Steady-state max voltage at all fail-safe IO pins" parameter for MCU_PORz in the "Absolute Maximum Ratings" table.

Regards,

Sreenivasa

Hi Board Designers, 

Inputs regarding PADCONFIG register ST_EN bit configuration
We expect hysteresis to always be turned on for every input that is controlled by a PADCONFIG register.
The default state of the ST_EN bit, which controls hysteresis, is “1” in every PADCONFIG register.
This bit should not be changed to disable hysteresis.
Disabling hysteresis makes the device susceptible to internal glitches which can cause unpredictable problems."

Customer has now confirmed that GPIO event counting works correct once hysteresis is enabled on the pin.

The minimum Input Slew Rate parameter defined in each Electrical Characteristics table is associated with long-term reliability. These parameters are not a function of the ST_EN bit. Note: We never expected software to disable hysteresis on any of the input pins. This is a mistake that needs to be fixed.

The minimum Input Slew Rate parameter defined in each peripheral timing section is a requirement to meet the respective peripheral timing parameters.

The device may not work as expected if you violate the minimum input slew rate limit defined in the respective peripheral timing section, but the device could be permanently damaged if you violate the minimum input slew rate limit defined in the respective Electrical Characteristics table. It is very important that you minimize the time a signal connected to one of our input buffers spends in the mid-supply region as it transitions from low to high or high to low.

Several of the AM62x GPIO have an internal debounce circuit in their path to the GPIO module, which can be configured to filter a noisy signal. This would be a better solution than applying an external RC filter that slows the signal slew rate. See Note1 attached to each GPIO Signal Description table in the datasheet to know which GPIO inputs have the debounce feature. GPIO1_30 does not have the debounce capability.

The Schmitt Trigger function (ST_EN) implemented in the input buffer only changes the output results of the input buffer, by filtering noise pulses that do not exceed the hysteresis.
The Schmitt Trigger function does not change how the input buffer is compromised when a system applies a slew rate to its input that is slower than defined in the datasheet.
The product must be designed to be in compliance with our datasheet requirements. If not, the non-compliance could reduce the life of the AM62x device.

Regards,

Sreenivasa

Hi Board Designers, 

I couldn't find a way to configure that bit using our SysConfig tool. Is that a missing feature? 

Meanwhile got feedback from the SysConfig team:

Yes, we are currently working on adding multiple additional PADCONF settings in SysConfig in the future releases (including ST_EN and others see below list). Also these will come up depending on the register reset and how the pad is defaultly set. Again here is the list of new settings that will appear in the tool with per pin specific configuration at reset.

Groups (additional settings):
- WAKEUP:
WKUP_EN
WK_LVL_POL
WK_LVL_EN

- DSLEEP:
DS_PULLTYPE_SEL
DS_PULLUD_EN
DSOUT_VAL
DSOUT_DIS
DS_EN

- ISO:
ISO_BYP
ISO_OVR

Main (basic settings):
- PULLTYPESEL
- PULLUDEN
- RXACTIVE
- ST_EN
- DEBOUNCE_SEL
- DRV_STR

Regards,

Sreenivasa

Hi Board Designers, 

Refer input related to IO behavior during cold start

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1532561/am2432-the-gpio-external-10k-resistor-is-pulled-up-but-the-gpio-pin-level-is-not-monotonic-during-the-power-on-process

(+) AM2432: The GPIO external 10K resistor is pulled up, but the GPIO pin level is not monotonic during the power on process - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

The IO cells implemented on pins Y7 and V7 were designed to operate at 1.8v or 3.3v mode. There is an internal supply detector mechanism that configures the IO in the appropriate mode based on the IO supply voltage level. During the mode transition from 1.8v mode to 3.3v mode or vice versa, it is possible for the IO to produce glitches on the signal. This doesn't cause any issue for the AM243x device.

You are correct. The IO cell monitors its own power rail and automatically changes from 1.8V mode to 3.3V mode as its IO power supply voltage continues to increase above 1.8V on its way to 3.3V. The opposite will happen as the IO power rail voltage decays. The IO cell will automatically change back to 1.8V mode as the IO supply voltage drops below 3.3V and approaches 1.8V.

The capacitor connected to pin L13 (CAP_VDDSHV5) doesn't have any effect on the IO cells associated with pins Y7 and V7, which are powered from pins R10, R8, and T9 (VDDSHV2). The glitch you see is not related to the value of any capacitor. It is a function of how the IO cell works. As mentioned in my previous post, there is nothing you can do to change how the IO cell works. However, connecting the wrong value capacitor can cause other problems.

Typically, a glitch on one of the AM243x pins is not an issue because the entire system is held in reset until all power supplies and clock sources are valid. You may need to insert a signal switch that blocks the glitch from propagating during power up if it is causing problems for your system.

Regards,

Sreenivasa

Hi Board Designers, 

Refer input related to IO leakage

When power is supplied and PORz is not released unexpected voltage leaks to UART0_RXD pin.

The IO buffers for UART0_RXD are off during power-up.

A pull is recommended when a trace is not connected and a signal is not being driven actively.

Voltage on an unconnected AM62Px pin is possible. The voltage observed on the pin is the result of leakage paths in the IO buffer, where the leakage can be as much as 10uA to either VSS or VDDSHV. This is normal as long as the leakage is not greater than 10uA. The resulting mid-supply voltage is not a problem for the AM62Px device as long as the receiver (input buffer) in the IO buffer remains off. However, the pin must be driven or pulled to a valid logic level anytime the receiver is turned on. Never allow the input of an enabled input buffer in the AM62Px device to float.

Note: We recommend external pulls to be used on any signal that connects AM62Px to the input of another device. The external pull is needed to hold the signal in a valid logic state until software turns on the associated AM62Px IO buffer such that it drives the signal to a valid logic state.

There is a good chance the AM62x device has been damaged by an Electrical Over-Stress (EOS) event if the IO buffer has more than 10uA of leakage with the output buffer and internal pull turned off.

There is a good chance this device is implemented using a more advanced process node than any of your previous devices. The more advanced process node uses significantly smaller geometries to implement on-die circuits, where the transistors are much smaller and have higher leakage.

We expect the IOs of any attached device to be powered from the same IO power source that is powering the AM62Px IOs associated with the attached device. 

The IOs associated with the AM62Px device are not fail-safe. This means no external circuit can source any potential greater than the potential applied to the respective IO power rail. See the "Steady-state max voltage at all other IO pins" parameter in the Absolute Maximum Ratings table in the datasheet, where the potential applied to a pin is limited to minimum of "-0.3V" and a maximum of "IO supply voltage + 0.3V".

The IO power rails of attached devices need to always have the same potential applied to prevent current injection into an IO that has a potential applied greater than the limits defined in the datasheet. For example, if one device is turned on the other device must be turned on, if one device is turned off the other device must be turned off. Their IO supplies also need to track as the power source ramps up or down. The best way to ensure this condition, is to power the IOs associated with both devices from the same power source.

The ESD protection circuits associated with an IO will turn on if the potential applied is greater than IO supply voltage+0.3V.  This condition will inject current from the external voltage source through the ESD circuits to the IO power rail. We do not allow injection current through the ESD protection circuits because they were only designed to protect the device from short-duration ESD events similar to what would be introduced by a Human Body Model to account for device handling and a Charged Device Model to account for PCB assembly equipment. The ESD protection circuits are not designed for steady-state DC current. They also were not designed to provide any system-level ESD protection once the device has been installed on a PCB.

The latest concern being discussed is a function of the power-down sequence and effect on the Ethernet PHY. However, there may be similar concerns associated with the power-up sequence and the effect on the AM62Px device.

The description seems to indicate the Ethernet PHY is powered from the same 3.3V power supply that is also sourcing the PMIC. If so, I suspect the Ethernet PHY receives power before the AM62Px device.  The Ethernet PHY may be applying potential to the AM62Px pins before they are powered. This would be the case if the Ethernet PHY has internal pull-ups that are turned on by default.

Regards,

Sreenivasa

Hi Board Designers, 

Refer input related to IO leakage

(+) AM625: I/O leakage current - Processors forum - Processors - TI E2E support forums

AM625: I/O leakage current

We only define one value for this parameter, and it is inclusive of all operating conditions.  We do not have additional data for specific operating conditions.

Please explain how this is creating a problem for your product design to see if I can offer any suggestions.

10uA is the limit for device pass/fall during final test, so there is a very small probability that you could get some devices that have up to 10uA of leakage. 

You may need to reduce the resistance of the pull-down to ensure the attached device is not enabled by the IO leakage.

Note: The more advanced process nodes have higher leakage due to the smaller transistors.

Regards,

Sreenivasa

Hi Board Designers, 

Refer below for E2Es relevant to GPIO

(+) AM62D-Q1: The AM62D-Mcasp interface configuration - Processors forum - Processors - TI E2E support forums

Voltage on an unconnected AM62Dx pin is possible. The voltage observed on the pin is the result of leakage paths in the IO buffer, where the leakage can be as much as 10uA to either VSS or VDDSHV. This is normal as long as the leakage is not greater than 10uA. The resulting mid-supply voltage is not a problem for the AM62Dx device as long as the receiver (input buffer) in the IO buffer remains off. However, the pin must be driven or pulled to a valid logic level anytime the receiver is turned on. Never allow the input of an enabled input buffer in the AM62Dx device to float.

Note: We recommend external pulls to be used on any signal that connects AM62Dx to the input of another device. The external pull is needed to hold the signal in a valid logic state until software turns on the associated AM62Dx IO buffer such that it drives the signal to a valid

(+) [FAQ] AM625: I/O leakage current - Processors forum - Processors - TI E2E support forums

10uA is the limit for device pass/fall during final test, so there is a very small probability that you could get some devices that have up to 10uA of leakage. 

You may need to reduce the resistance of the pull-down to ensure the attached device is not enabled by the IO leakage.

Note: The more advanced process nodes have higher leakage due to the smaller transistors.

(+) TDA4VM: LVCOMS 3.3V MODE Output High Voltage - Processors forum - Processors - TI E2E support forums

VOH and IOH are output parameters -- the output can source 6mA and still maintain a voltage above 2.4V.

A pull-up is normally used when the pin is used as an input; in this case, the output parameters are not applicable. The leakage current is 10uA and IHL is 2V, so that (3.3V - 2V) / 10uA = 120K. Because of tolerances, I would tend to use a somewhat smaller resistor than 120K, but this is how I understand the math.

(+) DRA821U: Pin handling and leakage current - Processors forum - Processors - TI E2E support forums

(+) TDA4VM: ADC Leakage Current - Processors forum - Processors - TI E2E support forums

(+) AM625-Q1: I/O lines internal clamping - Processors forum - Processors - TI E2E support forums

So that means that except for fail safe io pins, the rest of Io pins have the clamping diodes. Based on this Article by TI, is this correct? Clamp diodes: A one-way street

Most of the AM62x pins have similar clamp diodes used to protect the internal circuits from ESD events withing the limits defined in the respective ESD Ratings table. The pins listed as fail-safe in the Absolute Maximum Rating use other circuit methods to implement ESD protection that doesn't have the same dependance on the potential applied to the IO power rail.

Note: The ESD clamps/circuits are only designed to protect the device during handling and assembly on a PCB. They were not designed to provide any system-level ESD protection. You must add external ESD protection circuits to any signal which could be exposed to ESD events after the AM62x device has been placed on a PCB assembly.

(+) AM2434: GPIO max current sourced/sink on AM24 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

What is the GPIO current capability of the AM243

The explanation on GPIO is not part of the data sheet. Please refer to the TRM 

4.8 General Connectivity
4.8.1 General Purpose Input/Output (GPIO)

10.1.3 GPIO Interrupt Handling

12.2.1 General-Purpose Interface (GPIO)

According to the AM243x datasheet, the maximum current that can be sourced or sunk by a single GPIO pin is typically:

 4 mA for low-drive strength, 8 mA for medium-drive strength, 12 mA for high-drive strength, Can you please confirm

AM62A7-Q1: Interrupt Capable GPIOs ?

The AM243x datasheet only defines a single data point for current source/sink capability to achieve a specific output voltage (VOL or VOH) in the respective Electrical Characteristics section of the datasheet. The system designer will need to use the device IBIS model to determine the output voltage for any load other than the values defined in the IOL and IOH parameters.

Note: We only expect our digital output buffers to source CMOS inputs which have a minimum amount of leakage current when driving a steady-state logic level. We do not expect our digital outputs to drive any significant steady-state current.

See the table note associated with the IOL and IOH parameters.

Regards,

Sreenivasa

Hi Board Designer,

May i know what is the period for functional clock as specified in GPIO timing requirement?

Refer below:

HFOSC0_CLKOUT -- This is the HFOSC placed on the board. Usually 25 MHz for Sitara SoC boards.
MAIN_SYSCLK0 -- 500 MHz (Derived from MAIN PLL 0 and this is not allowed to be changed in DM firmware)
MCU_SYCLK0 -- 400 MHz (Derived from MCU PLL 0 and this is not allowed to be changed in DM firmware)

For other clocks, the defaults can be found here

AM62PX PLL Defaults — TISCI User Guide

https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62px/pll_data.html

Note: You need to use the Clock tree tool to get the clock period for each peripheral where the functional clock period is reference.

Regards,

Sreenivasa

Hi Board Designer,

Inputs related to max frequency:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1551807/am6442-signal-frequency/5975519

Can you help me to find the max. frequency for I2C, SPI, UART and GPIO's signals of the AM6442 processor

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1549638/am620-q1-input-slew-rate/5966524?tisearch=e2e-sitesearch&keymatch=MAIN_SYSCLK0#

Regards,

Sreenivasa

Hi Board designers,

Refer below interaction on floating IOs

AM62A3-Q1: Floating voltage of the G21 pin at startup

Voltage on an unconnected AM62Dx pin is possible. The voltage observed on the pin is the result of leakage paths in the IO buffer, where the leakage can be as much as 10uA to either VSS or VDDSHV. This is normal as long as the leakage is not greater than 10uA. The resulting mid-supply voltage is not a problem for the AM62Dx device as long as the receiver (input buffer) in the IO buffer remains off. However, the pin must be driven or pulled to a valid logic level anytime the receiver is turned on. Never allow the input of an enabled input buffer in the AM62Dx device to float.

Note: We recommend external pulls to be used on any signal that connects AM62Dx to the input of another device. The external pull is needed to hold the signal in a valid logic state until software turns on the associated AM62Dx IO buffer such that it drives the signal to a valid logic state

At the start-up of the SoC, a floating voltage of about 100mV is observed on pin G21. Is this normal operation? Why is it floating?

Ether PHY supplier says maybe there is PU(min 30k / max150k)

If so, we can understand why 100mV floating voltage happens at Ether PHY side by following our calculation.

Could you please add a pulldown on the SOC output pin without connecting to the EPHY reset input 

The result is there is no floating voltage. So, I have confirmed that it is as you explained.

So, now we understand why floating voltage happens at SoC and Ether side.

Regards,

Sreenivasa

Hi Board designers,

Refer below information elated to:

Debounce support

Data sheet reference:

Signal Descriptions section

At the end of the peripheral signal description, debounce support is mentioned.

Pin Attributes

Hysteresis

HYS: Indicates if the input buffer associated with this I/O has hysteresis:

• Yes: With hysteresis

• No: Without hysteresis

• An empty box means Not Applicable.

Regards,

Sreenivasa