AM62P: "Request for Review: AM62P-Based Schematic Design for Hardware Validation"

Hello Vandana

Thank you for the schematic review request.

Can you please confirm if you have been working with any of the TI sales.

If yes, please work with the TI sales to submit schematic review request.

The below documents can be referenced to perform self-review

Recommended References for self-review and design of custom board
AM62P
Data sheet
AM62Px Sitara Processors datasheet 
www.ti.com/.../sprsp89
Hardware Design Considerations
www.ti.com/.../sprada9
DDR Board Design and Layout Guidelines
www.ti.com/.../sprad66
Schematic Design and Review Checklist for AM62Px processor family
www.ti.com/.../spradn4
Schematic Design and Review Checklist combined for sitara processor families
www.ti.com/.../sprad21
Errata
www.ti.com/.../sprz574

Schematic review request (internal)
e2e.ti.com/.../4661966
AM62P Schematic checklist
e2e.ti.com/.../faq-am625-am623-am62a-am62p-am62d-q1-am64x-am243x-design-recommendations-custom-board-hardware-design---schematics-review-checklists

AM62P Schematic self-review
e2e.ti.com/.../faq-am62p-am62p-q1-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review
e2e.ti.com/.../faq-am625-am623-am62a-design-recommendations-commonly-observed-errors-during-custom-board-hardware-design-sk-schematics-updates-for-design-update-note
e2e.ti.com/.../faq-am625-am625-am623-am62a-am62p-am62d-q1-am64x-am243x-design-recommendations-custom-board-hardware-design---list-of-errors-observed-during-customer-schematics-review
e2e.ti.com/.../faq-am625-am623-am62a-am62p-am62d-q1-am64x-am243x-design-recommendations-custom-board-hardware-design---queries-related-to-soc-data-sheet-pin-attributes

Frequently Asked Questions FAQs
e2e.ti.com/.../faq-custom-board-hardware-design---master-complete-list-of-faqs-for-all-sitara-processor-am62x-am64x-am243x-am335x-families
e2e.ti.com/.../faq-am62p-am62p-q1-custom-board-hardware-design---faqs-related-to-processor-collaterals-functioning-peripherals-interface-and-starter-kit
e2e.ti.com/.../faq-am62x-am64x-custom-board-hardware-design-how-to-handle-used-unused-pins-peripherals-e-g-gpios-serdes-usb-csi-mmc-emmc-sd-card-csi-oldi-dsi

Frequently Asked Questions FAQs for schematics D-Note, R-Note
e2e.ti.com/.../faq-am62p-am62p-q1---custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62p-lp-schematics

Downloadable design files on TI.com list for SK
SK-AM62P-LP Design Package Folder and Files List (Rev. A)
www.ti.com/.../sprt780
https://www.ti.com/lit/zip/sprr487

Regards,

Sreenivasa

Thanks for sharing the documents and reference links. To make the review more effective, could you please highlight any specific areas in the design where you'd like input or feel there might be room for improvement?

That way, I can focus on the most relevant parts and provide more meaningful feedback. With the current volume of material, it’s a bit challenging to pinpoint what exactly needs attention.

Hello Vandana

Thank you .

Can you please answer the below just in case you missed.

Kallikuppa Sreenivasa said:

Can you please confirm if you have been working with any of the TI sales.

If yes, please work with the TI sales to submit schematic review request.

Regards,

Sreenivasa

Hello Vandana

Vandana D said:

To make the review more effective, could you please highlight any specific areas in the design where you'd like input or feel there might be room for improvement?

The checklist is categorized into section for you to focus on the section and peripheral of interest.

Regards,

Sreenivasa

Hello Vandana

I did a quick check and observed the bootmode could be optimized

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1391522/faq-am625-am623-am644x-am243x-am62a-am62p-am62d-q1-am62l---bootmode-implementation-without-buffers

When bootmode buffers are not used you could use only pullups or pulldown to configure and delete the DIP switch. This is the recommended approach.

Pls follow the above FAQ.

SOC_I2C1_SCL connected to U96 has a pullup near the SOC, 

and 

The recommendation is to pull the I2C at one location and match the supply rail to the IO supply for IO group VDDSHV0.

Regards,

Sreenivasa

Hello Vandana

I missed adding that the fastest i can mark these quick comments and share is end of next week.

I am also waiting for you to confirm if you are working with TI sales.

Regards,

Sreenivasa

Dear Sir,

Thank you for all the valuable inputs. We truly appreciate your support and suggestions.

Once we complete the review process, we will proceed to engage with the TI Sales team for the next steps.

Best regards,

Vandana D

Hello Vandana

Thank you.

I observed the below error while implementing the SD card power reset load switch.

Not sure from where you got the symbol for load switch where the 2 pins are swapped?

Customer

AM62P SK

Regards,

Sreenivasa

Hello Vandana,

Please refer below FAQ when reusing SK design files for custom board design:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1304794/faq-am62p-am62p-q1-custom-board-hardware-design---reusing-ti-sk-evm-design-files

Regards,

Sreenivasa

Hello Vandana,

Please refer below FAQ when reusing SK design files for custom board design:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1304794/faq-am62p-am62p-q1-custom-board-hardware-design---reusing-ti-sk-evm-design-files

Regards,

Sreenivasa

Hello Vandana,

Please refer below

The net name is same for input and output.

Regards,

Sreenivasa

Hello Vandana,

Can you please help me understand the use case for paralleling  2 x 120R.

I assume you wanted to parallel 2 x 240R.

Can you please confirm.

Regards,

Sreenivasa

Noted. Please let me know if any other changes are required.

Sir, We intended to connect a 120-ohm resistor in parallel with a 60-ohm resistor, which will be terminated as needed.

Hello Vandana, 

Thank you. I am not sure i understand the use case for 120 in parallel to 60R. 

Regards.

Sreenivasa 

Hello Vandana, 

I may have a few additional observations based on quick review.

Vandana D said:

Noted. Please let me know if any other changes are required.

I will share the same by early next week.

Regards,

Sreenivasa

Hello Vandana, 

Vandana D said:

Noted. Please let me know if any other changes are required.

CSI AND DSI IS NOT USED IN THIS DESIGN

I see the above note. Please note the connectivity requirements when these peripherals are not you.

In case you want to provision, you should route these signals as 100R differential pairs and terminate to a connector similar to the connections you may be doing when using the peripheral.

Regards,

Sreenivasa

Thank you for Optional CSI/DSI Interface Layout Recommendations. I’ll be waiting for any further updates.

Hello Vandana, 

Thank you.

Will let you know if i have any findings this week.

Please read through the data sheet pin attributes, pin connectivity, hardware design consideration document and the schematic review checklist that oi listed for any issues that may be there.

I will be supporting only a quick review.

Regards,

Sreenivasa

Hello Vandana, 

Is the schematics for the core board partial of full - any thoughts if you plan to use the GPMC interface ?

regards,

Sreenivasa

Sir, I’ve shared the complete schematic file and We're not using any additional GPMC interface in our design.

Hello Vandana, 

Thank you for the quick response, appreciated.

Regards,

Sreenivasa

Hello Vandana, 

I did some quick check and added my comments to the schematics.

Please review and update the comments.

General Notes (For customer to review)

8512.hinduja_cluster_mpu_board_v1.2.pdf

Regards,

Sreenivasa

Hello Vandana, 

Please note i have done some quick review and added my comments. 

Please work with TI sales for any additional support of follow the collaterals i shared in the initial reply.

Some general guidelines 

We have reviewed the schematics to the best. Since the implementation and design flow is customer specific,
there may be similar updates that customer will have to review and make the updates.
Verify all the core, analog and IO supplies for the SOC are connected to the recommended supply voltage levels
When Adjustable DC/DC or LDO are used, verify the resistor divider ration matches the required output voltage
Ensure all the pullups connected to the SOC are pulled up to the correct I/O voltage (matches with the IO supply referenced for the specific IO groups)
Verify the device selection section of the data sheet based on the requirement to confirm the device selection
Verify the pin configuration for the memory interface, communication and IO interfaces using the sysconfig - pinmux tool
Verify the mapping of the schematics symbol pin number and name with the pin name and number as per the pin attributes section of the data sheet
Any SoC pad that has a trace connected and not being actively driven needs an external parallel pull
Verify Device specific Errata for allowed bootmode configuration and erratas affecting the functionality
Verify Pin connectivity table of the data sheet for connecting any unused pins or peripherals including supplies
Please read through the SOC data sheet pin connectivity requirements and ensure the recommendations are followed
Resistor divider tolerance for discrete DC/DC or LDO output supply feedback is 1% for improved output accuracy
Note the I2C interface exceptions and pin connectivity requirements
Add provision to isolate and probe the OBSCLK for testing

Common SOC LVCMOS IO interface guidelines (For customers to review and make updates)
1. Most of the SOC IOs are not fail-safe. No input should be applied before supply ramps
2. SOC LVCOMOS IOs have slew rate requirements specified, applying a slow ramp input or connecting a cap at the input is not recommended
3. Connecting a cap load >22pF at the LVCMOS IO output is not recommended. DNI cap or perform simulations based on the use case.
4. SOC IO buffers are off during Reset. A pull is required near to the attached device being driven by the SOC IO that could float
5. Any SOC IO that has a trace connected needs a parallel pull. When adding pull is not feasible, ensure the traces are routed away from noisy signals
6. Connecting SOC IOs that have alternate function that can be configured directly to supply or ground is not allowed or recommended (including bootmode inputs).
(Customer could have bug with their firmware and mis-configure these LVCMOS GPIOs that were intended to be inputs, to be outputs driven logic high instead)
7.Verify cap loading of the SOC output (when any cap value >22 pF (use case dependent, max value) is connected, customer needs to simulate),
slew rate of the input signal (LVCMOS input slew should be 1000 ns or less), IO compatibility and fail-safe operation between the SOC IOs and attached devices

Regards,

Sreenivasa

Hello Vandana, 

In the debug board, i see a 40-pin connector that interfaces to the processor board (assume)

I do not see a 40-pin connector on the processor board.

help me understand how the 2 board are connected together.

Regards,

Sreenivasa

5700.hinduja_daughter_board.pdf

Sir, Thank for all the time,effort and helpful feedbackon our MPU main board design.

I've now attached the daughter board design, which was unintentionally left out earlier. Just to clarify, the 40-pin connector is solely meant for the OLDI display and isn’t used for debugging.

Hello Vandana, 

Thank you and happy to support.

Can you please help me understand how the daughter board connects to the processor board 

Which connector from Daughter board connected to which connector of the MPU board. Is the connection through a cable or the boards are interconnected through a connector.

Regards,

Sreenivasa

Sir,

We are using connectors J7 and J8 (page 4 of the daughter board documentation) for the interaction between the main board and the daughter board.

Hello Vandana, 

Thank you 

To which connectors on the main board does J7 and J8 of the daughter connect to?

Regards,

Sreenivasa

Sir, 

The pin count of connectors J1 and J2 from the main board (page 6) needs to be changed since the main board currently has 32 pins, while the daughter board has 40 pins. This will be updated based on further requirements.

Thank you.

Hello Vandana, 

Thank you and noted.

Regards,

Sreenivasa

Sir,

I Noticed you mentioned the termination resistor package size—could you confirm what's needed? We're currently using 0402package with 1/10W.

Also, a quick reminder to review our daughter board schematic when you get a chance.

Regards,

Vandana D

Hello Vandana,

Thank you.

You need to refer to the media converter design

https://www.ti.com/lit/ug/snlu289/snlu289.pdf

R18, R25 2 CRCW08051M00JNEA RES, 1.0 M, 5%, 0.125 W, AEC-Q200 Grade 0, 0805 0805_HV

C7, C28 2 GRM31BR73A472KW01L CAP, CERM, 4700 pF, 1000 V, +/- 10%, X7R, 1206 1206

Data sheet reference

https://www.ti.com/lit/ds/symlink/dp83tg720r-q1.pdf

Regards,

Sreenivasa

Hello Vandana,

Vandana D said:

Also, a quick reminder to review our daughter board schematic when you get a chance.

The signals between the SOM board and the daughter board does not map.

Please provide a table for the signals going from the SOC board to daughter board to review.

Regards,

Sreenivasa

Sure Sir, Give us some time to provide you the table for the signals going from the SOC board to daughter board.

Regards,

Vandana D

Hello Vandana,

Thank you and understand.

Regards,

Sreenivasa

Hi Sir,

Just following up to check if our design [daughter board] has been reviewed.

Regards,

Vandana D

Hello Vandana, 

Thank you.

I was waiting for you to share the signal mapping table.

Regards,

Sreenivasa

Hello Vandana, 

I had a quick look at the daughter card schematics.

The Schematics is mostly discrete power architecture.

I can have a quick look.

In the meantime, can you please add an E2E query (for each of the DC/DC) with the TI device title + request for review.

Do not mention the SOC number.

The Query will be assigned to the right PL and experts to review.

Regards,

Sreenivasa

Sir,

Thank you for all the support, feedback, and valuable suggestions — I truly appreciate it and will proceed accordingly with new E2E query.

Regards,

Vandana D

Hello Vandana, 

Thank you.

I have a few observations that i will share today or tomorrow.

Regards,

Sreenivasa

0871.hinduja_daughter_board.pdf

Hello Vandana, 

Thank you.

I added quick review comments from my side.

Please review and make required updates and also work with relevant PLs to get the implementation reviewed.

Regards,

Sreenivasa