AM6422: Usage of SERDES REFCLK as an output

Luke

Part Number: AM6422

Tool/software:

Hi team,

It is my and the customer's understanding that they can utilize the SERDES REFCLK as an output on the AM6422 due to the updates in the errata. However, other than showing the signal pair as I/O in various tables and figures, there is nothing that talks about using SERDES REFCLK as an output in the datasheet or TRM. Datasheet section 6.10.4.1, Input Clocks / Oscillators, calls it an optional reference clock input for PCIe and 6.10.4.2, Output Clocks, does not mention it.

Where is SERDES0_REFCLK0 used as an output discussed other than the errata? Sourcing the PCIe reference clock from the CPU and providing to the FPGA would be desirable for them.

Is an output clock the default setting for the SERDES REFCLK? Does anything need to be programmed to generate the output clock? What is inside the device and what does the PWB need to provide (series resistors, resistors to ground)?

Thanks,
Luke

3 months ago

0 Kallikuppa Sreenivasa 3 months ago

TI__Guru**** 191839 points

Hello Luke,

Thank you for the query.

Luke said:
what does the PWB need to provide (series resistors, resistors to ground)?

Please refer to the AM64x EVM schematics and Am64x schematics checklist

• Clock output from the processor The processor clock output can be connected as the clock input to the add-on card. Place 50Ω (49.9Ω) resistor at the clock output terminals (P and N) with respect to ground closer to the processor.

https://www.ti.com/lit/an/spracu5d/spracu5d.pdf

Provision for series resistor close to the clock output is recommended.

In the EVM the processor is configured for external clock as default. Based on this i suspect the default configuration is the processor clock being an input.

Our expert is out of office this week.

I will check internally and update. Please expect some delay in response.

Regards,

Sreenivasa

0 Luke 3 months ago in reply to Kallikuppa Sreenivasa

TI__Expert 3800 points

Hi Sreenivasa,

Thanks for the initial feedback! Looking forward to hearing back more information on this one.

Understood on the delay.

Best,

Luke

0 Kallikuppa Sreenivasa 3 months ago in reply to Luke

TI__Guru**** 191839 points

Hello Luke,

Thank you.

I will follow-up early next week and update you.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 191839 points

Hello Luke,

As i wait for the expert, below FAQs could be used as reference:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1503363/am6442-generating-pcie-clock-from-am6442

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1421341/am6412-serdes0_refclk-selection

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1332399/am6442-how-to-configure-serdes0_refclk-as-an-output-and-route-internal-pcie-reference-clock-to-them

Regards,

Sreenivasa

0 Luke 3 months ago in reply to Kallikuppa Sreenivasa

TI__Expert 3800 points

Hi Sreenivasa,

Thanks for sharing these posts. They look useful! Any further info from the expert?

Best,

Luke

0 Kallikuppa Sreenivasa 3 months ago in reply to Luke

TI__Guru**** 191839 points

Hello Luke,

Thank you/

Any thoughts on the software customer is using - Linux?

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 191839 points

Hello Luke,

I have added the information i received.

We pulled up the MCU+SDK to determine what could be done, and if the customer is using MCU+SDK as code base, it seems like customer would need to just define in ti_drivers_config.c “.refclk_mode = PCIE_REFCLK_MODE_INT_NOSSC_OUTEN” as that would set needed flags to enable.

Linux

Is customer is using Linux as I believe the SDK will by default source RefClk out to pins from being generated our SOC’s PCIe internal clock.

there are at least a couple registers which are related to control the refclk direction. Linux user only need to modify kernel devicetree for the refclk direction.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 191839 points

Hello Luke,

Additional inputs from the expert:

I don’t believe the register for Phy_en_refclk is available in the TRM

Regards,

Sreenivasa

+1 Dominic Rath 3 months ago in reply to Kallikuppa Sreenivasa

Mastermind 7450 points

Hi All,

Kallikuppa Sreenivasa said:
We pulled up the MCU+SDK to determine what could be done, and if the customer is using MCU+SDK as code base, it seems like customer would need to just define in ti_drivers_config.c “.refclk_mode = PCIE_REFCLK_MODE_INT_NOSSC_OUTEN” as that would set needed flags to enable.

with MCU+ SDK you can select the RefClk configuration from a drop-down. Be aware that this includes combinations that TI says are not supported (internal RefClk with SSC).

Kallikuppa Sreenivasa said:
I don’t believe the register for Phy_en_refclk is available in the TRM

The whole SerDes is not documented in the AM64x TRM, but an older version of the J7200 (spruiu1a) did include them. I believe not all registers have the same address in the AM64x, but the MCU+ SDK code tells you where the registers are, and spruiu1a tells you what the bits mean.

Regards,

Dominic

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AM6422: Usage of SERDES REFCLK as an output