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EMAC MII custom configuration question.

Anatoly Odler
Expert 1870 points

Hello,

Our custom project board has secured C6748 on it.

We have built the following setup for the Ethernet communication:

Where Reverse MII is third party manufacturer board, which performs Ethernet over USB conversion, and the Normal MII is the EMAC of the C6748.

Reverse MII board is powered by a PC via USB and the PC detects it as a network card (as expected).

If we connect the two boards( while the Reverse MII board is plugged by USB), the DSP crashes, so we cannot debug via the JTAG, and we have to reset the C6748.

In addition, we cannot connect via JTAG debugger when the two boards are connected (and powered).

As we checked, the connections are properly configured physically, both the EMAC and the JTAG parts, as well as the EMAC is properly configured by software.
We performed tests, and got that the TXCLK and RXCLK of the C6748 somehow crash the device, despite that the signal is standard MII 25 MHz.
  1. What can crash the DSP in this setup? If it is the TXCLK or RXCLK, then why and are they legally connected?
  2. Is this setup workable for the EMAC MII configuration to perform data transmission in general?
Thank you, Anatoly.
  • 0
    Prodigy 20 points

    Hello Anatoly,

    I think, we have a similar set, as what you described above, on our project.

    I learnt from the HW team that, on our board, the PHY hardware generates the MII clock, for the MDIO.

    what you can do is: 

    Maybe unconnect your RxClock and TxClock, and use a Low Frequency Generator to generate a separate clock on each one, then, you will know what one is causing the problem.

    I think, oneof them (Tx clock), doesn't have to be imposed by your Reversed MII device.

    so, i think, you will have to unconnect them !

    I hope, this gives you some lead for your issue.

    Besides this, i see that you think having well configured your EMAC module:

    For my part (in a post that i created today), we have a problem configuring the EMAC !

    we succeded to have frames arriving into it: RXGOODFRAMES statistics register is incremented by the right number of frames sent by our test bench,  but, we don't have any data reaching the RAM buffers.

    we placed the Packet descriptors in the CPPI ram, and in intarnal RAM we have the data buffers (pointed by descriptors):

    do you have any idea about the issue ?

    do you have any working example of EMAC configuration ?

    Thank you in advance.

    Salah.