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dm816x DDR3 intialization

Ankit Thakkar
Prodigy 90 points

Hello,

We are working upon dm816x processor.

In couple of boards when the processor is connected to JTAG and in CCS when we try to intialize the DDR3 interface, the JTAG communication fails.

Though this problem is specific to two boards. It happens only when it tries to initialize EMIF for DDR3.

The text files containing the log for working board and faulty board are mentioned below.

Any one have faced similar issues?

Regards,

Ankit

Log for working board

CortexA8: Output:     Netra Main PLL Init is in Progress, Please wait .....
CortexA8: Output:     Netra Main PLL Init is Done .....
CortexA8: Output:     Device type is GP
CortexA8: Output:     Netra Main PLL Init is in Progress, Please wait .....
CortexA8: Output:     Netra Main PLL Init is Done .....
CortexA8: Output:     Netra DDR PLL Init is in Progress for 400 MHz DDR Clock, Please wait .....
CortexA8: Output:     Netra DDR PLL Init is Done .....
CortexA8: Output:     Netra DDR2/3 PRCM Init is in progress .....
CortexA8: Output:     Netra DDR2/3 PRCM Init is Done .....

CortexA8: Trouble Writing Memory Block at 0x4c000010 on Page 0 of Length 0x4: (Error -2130 @ 0x4C000010) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Release 5.0.333.0)
 
CortexA8: Trouble Reading Register CP15_CONTROL_REGISTER: (Error -2131 @ 0x20013F00) Unable to access device register. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Release 5.0.333.0)

CortexA8: Trouble Reading Register CP15_MMU_XLATION_TABLE_BASE_CONTROL: (Error -2131 @ 0x20023F40) Unable to access device register. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Release 5.0.333.0)

CortexA8: Trouble Reading Register CP15_MMU_XLATION_TABLE_BASE_0: (Error -2131 @ 0x20023F00) Unable to access device register. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Release 5.0.333.0)

CortexA8: Trouble Reading Register CP15_MMU_XLATION_TABLE_BASE_1: (Error -2131 @ 0x20023F20) Unable to access device register. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Release 5.0.333.0)

Log for problamtic board

CortexA8: Output:     Device type is GP
CortexA8: Output:     Netra Main PLL Init is in Progress, Please wait .....
CortexA8: Output:     Netra Main PLL Init is Done .....
CortexA8: Output:     Netra DDR PLL Init is in Progress for 400 MHz DDR Clock, Please wait .....
CortexA8: Output:     Netra DDR PLL Init is Done .....
CortexA8: Output:     Netra DDR2/3 PRCM Init is in progress .....
CortexA8: Output:     Netra DDR2/3 PRCM Init is Done .....
CortexA8: Output:     Initializing EMIF1 .....
CortexA8: Output:     Netra EMIF Init is Done @ 400 MHz Clock Rate.....
CortexA8: Output:     PRCM for OCMCRAM0/1 Initialization in Progress
CortexA8: Output:     OCMCRAM0 & OCMCRAM1 Accesses are PASSED
CortexA8: Output:     PRCM for OCMCRAM0/1 Initialization Done

  • 0
    TI__Guru**** 170625 points

    Hi Ankit,

    This looks like HW design issue. Did you cross check the layout? You stated that only two boards are not working correctly, and we need to know how many boards are working correctly?

    Regards,

    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 90 points

    Hello Pavel,

    We have four boards, out of which two boards are working fine.

    In one board DDR1 controller interface works fine. (DDR0 controller interface is dead)

    In one board both DDR controller interfaces are dead.

    I traced the gel file for the same and found that it is not able to program the EMIF registers for refresh rate of DDR.

    I checked with the layout as well. But I dont see any problems in layout.

    Regards,

    Ankit

  • 0 in reply to Ankit Thakkar
    Guru 31670 points

    Did you compare the board revisions? I have faced similar issue with older revisions (REV C) and it works for the latest revisions.

  • 0 in reply to Renjith Thomas
    TI__Guru**** 170625 points

    Hello Ankit,

    My TI EVM DM8168 (from Spectrum Digital) is TI8168-GP 2.1 REV J. I am using CCS/JTAG with GEL file evm816x.gel v1.02. And it works fine for me, this is the log:

    CortexA8: GEL Output: EVM816x Startup Sequence

    CortexA8: GEL Output: PRCM Setup Complete
    CortexA8: GEL Output: Configuring Pad Functions...
    CortexA8: Output:     Main PLL Init is in Progress, Please wait .....
    CortexA8: Output:     Main PLL Init is Done .....
    CortexA8: Output:     EVM816x DDR PLL Init is in Progress for 796 MHz DDR Clock, Please wait .....
    CortexA8: Output:     DDR3 Selected.
    CortexA8: Output:     DM816x DDR PLL Init is Done .....
    CortexA8: Output:     EVM816x DDR2/3 PRCM Init is in progress .....
    CortexA8: Output:     EVM816x DDR2/3 PRCM Init is Done .....
    CortexA8: Output:     Initializing EMIF1 .....
    CortexA8: Output:     DDR3 SWLEVELING DONE FOR EMIF0
    CortexA8: Output:     DDR3 SWLEVELING DONE FOR EMIF1
    CortexA8: Output:     DM816x EMIF Init is Done @ 796MHz Clock Rate.....
    CortexA8: GEL Output: Startup Complete.

    CortexA8: GEL Output: GEL Reset

    This works when the EVM is not booted at all, or the boot process is interrupted in the u-boot TI8168_EVM#.

    BR

    Pavel

  • 0
    Prodigy 70 points

    The time out indicates that the leveling is not complete. The DDR EMIF register configuration might not be correct. You have to calculate the register setting for target memory.

    This link might help

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

  • 0 in reply to Madhura IA
    Prodigy 170 points

    Hello Ankit/Renjith/Pavel,

      We are working on DM8168 based design. And getting same problem as Ankit got. Earlier it was working device, but suddenly due to some problem it stops working. so i was trying to debug. While loading GEL file PRCM is ok, after that while DDR initialization time it fails.Attaching the log for the same. We tried to prob ddr reset signal,In that DDR0 signal is ok but DDR1 reset signal is not releasing it is always low It looks like ddr is not initializing.

       Please help us for the same.

      

    5367.2260.DM8168 DDR log.txt
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    CortexA8: GEL Output: EVM816x Startup Sequence
    CortexA8: GEL Output: PRCM Setup Complete
    CortexA8: GEL Output: Configuring Pad Functions...
    CortexA8: Output: Main PLL Init is in Progress, Please wait .....
    CortexA8: Output: Main PLL Init is Done .....
    CortexA8: Output: EVM816x DDR PLL Init is in Progress for 400 MHz DDR Clock, Please wait .....
    CortexA8: Output: DDR3 Selected.
    CortexA8: Output: DM816x DDR PLL Init is Done .....
    CortexA8: Output: EVM816x DDR2/3 PRCM Init is in progress .....
    CortexA8: Output: EVM816x DDR2/3 PRCM Init is Done .....
    CortexA8: Trouble Writing Memory Block at 0x4c000010 on Page 0 of Length 0x4: (Error -2130 @ 0x4C000010) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
    CortexA8: GEL: Error while executing OnTargetConnect(): target access failed at *((unsigned int *) (0x4C000000+0x10))=(unsigned int) (0x10000000|SDREF) [evm816x 400.gel:325] at EMIF4P_Init(0x0CCCE524, 0x30308023, 0x009F82CF, (0x10000C30&0xfffffff), 0x62A41032, 0x0000030B) [evm816x 400.gel:1308] at Setup_DDR() [evm816x 400.gel:47] at OnTargetConnect() .
    CortexA8: Failed Software Reset
    CortexA8: GEL Output: GEL Reset
    CortexA8: Trouble Writing Memory Block at 0x40300800 on Page 0 of Length 0x4bc: (Error -1204 @ 0x3D5B) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
    CortexA8: Unable to terminate memory download: NULL buffer pointer at 0x3a9f
    CortexA8: GEL: File: D:\ccs_workspace\2309\Debug\2309.out: Load failed.
    CortexA8: Error: (Error -1203 @ 0x3D5B) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    =====CCS log of DM8168 processor =====================

    CortexA8: GEL Output: EVM816x Startup Sequence

    CortexA8: GEL Output: PRCM Setup Complete
    CortexA8: GEL Output: Configuring Pad Functions...
    CortexA8: Output: Main PLL Init is in Progress, Please wait .....
    CortexA8: Output: Main PLL Init is Done .....
    CortexA8: Output: EVM816x DDR PLL Init is in Progress for 400 MHz DDR Clock, Please wait .....
    CortexA8: Output: DDR3 Selected.
    CortexA8: Output: DM816x DDR PLL Init is Done .....
    CortexA8: Output: EVM816x DDR2/3 PRCM Init is in progress .....
    CortexA8: Output: EVM816x DDR2/3 PRCM Init is Done .....
    CortexA8: Trouble Writing Memory Block at 0x4c000010 on Page 0 of Length 0x4: (Error -2130 @ 0x4C000010) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
    CortexA8: GEL: Error while executing OnTargetConnect(): target access failed at *((unsigned int *) (0x4C000000+0x10))=(unsigned int) (0x10000000|SDREF) [evm816x 400.gel:325] at EMIF4P_Init(0x0CCCE524, 0x30308023, 0x009F82CF, (0x10000C30&0xfffffff), 0x62A41032, 0x0000030B) [evm816x 400.gel:1308] at Setup_DDR() [evm816x 400.gel:47] at OnTargetConnect() .
    CortexA8: Failed Software Reset
    CortexA8: GEL Output: GEL Reset
    CortexA8: Trouble Writing Memory Block at 0x40300800 on Page 0 of Length 0x4bc: (Error -1204 @ 0x3D5B) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
    CortexA8: Unable to terminate memory download: NULL buffer pointer at 0x3a9f
    CortexA8: GEL: File: D:\ccs_workspace\2309\Debug\2309.out: Load failed.
    CortexA8: Error: (Error -1203 @ 0x3D5B) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
    CortexA8: Error: (Error -1044 @ 0xFFFFEC70) The emulator reported an error. Confirm emulator configuration and connections, reset the emulator, and retry the operation. (Emulation package 5.0.747.0)
    CS_DAP_DebugSS: Error: (Error -5008 @ 0xFFFFEC70) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 0.0.0.0)

    ======================================================

     

    Thank you in advance! 

    Regards,

    Pragnesh Virani

     

  • 0 in reply to pragnesh virani
    TI__Guru**** 170625 points

    Pragnesh,

    pragnesh virani said:
    While loading GEL file PRCM is ok, after that while DDR initialization time it fails.

    Which GEL file you are using?

    pragnesh virani said:
    CortexA8: Trouble Writing Memory Block at 0x4c000010 on Page 0 of Length 0x4: (Error -2130 @ 0x4C000010) Unable to access device memory.

    The 0x4C000010 address is from the DDR EMIF0 register map, SDRAM Refresh Control Register - SDRRCR.

    Make sure you have enabled the DDR EMIF0 clock signals from the device PRMC. Try to reduce the DDR3 frequency to check is stability improves. Consider also the software leveling.

    See the below e2e threads for some info:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/141133.aspx

    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/250461.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/180437.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/369055.aspx

    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/125794.aspx

    Best regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 170 points

    Dear Pavel,   

      Thanks for your replay!

     I am using evm816x.gel  of Version 1.02. Attaching GEL file.

     And I got some clue over this,It's Bit strange, I was trying  to load GEL file with different DDR speed in that with 400,531,756, 783, 796 MHz DDR1 RESET signal is not initiating but with 621, 634, 648, 675, 702, 729Mhz frequency it's initiates and processor sends reset to DDR ,so getting control over the same. Question is why it is not loading with lower and higher Frequency?

     And one more problem getting is, I was trying to fill 0XFFFFFFFF data to some memory location. In that lower bit is not writing properly to some location.Attaching the snap of memory browser. 

    Please give some advice for the same!

    8306.evm816x.gel

    Thanks,

    Pragnesh Virani

  • 0 in reply to pragnesh virani
    Prodigy 170 points

    Dear Pavel, 

         We have disabled DDR interleaving in GEL file.

    /*Program the DMM to Access EMIF0 and 1*/
    WR_MEM_32(DMM_LISA_MAP__0, 0x80500100); // Interleaved 1GB section from 0x80000000
    WR_MEM_32(DMM_LISA_MAP__1, 0xC0500120); // Interleaved 1GB section from 0xC0000000

    WR_MEM_32(DMM_LISA_MAP__2, 0x80500200);
    WR_MEM_32(DMM_LISA_MAP__3, 0xC0500220);

      After changing this able to write correct data to on both DDR ranks (i.e. to 0X80000000 and to 0XC0000000) and we have tried with some test pattern for DDR, it is passing. (FYI ,Here Previously 0th bit was not writing proper).

    So we have modified same to DMM_LISA_MAP Registers in u-boot, But status is same. Can you give some suggestion over this?

    Or is there anyway to load u-boot to DDR through CCS?

    Regards,

    Pragnesh Virani

     

  • 0 in reply to pragnesh virani
    TI__Guru**** 170625 points

    Pragnesh,

    pragnesh virani said:
    We have disabled DDR interleaving in GEL file.

    pragnesh virani said:
    After changing this able to write correct data to on both DDR ranks (i.e. to 0X80000000 and to 0XC0000000) and we have tried with some test pattern for DDR, it is passing. (FYI ,Here Previously 0th bit was not writing proper).

    This seems to be DDR3 HW design issue. Please check:

    DM816x datasheet, 9.3 DDR2 and DDR3 Memory Controller

    DM816x EVM DDR3 schematics from Spectrum Digital

    DM816x EVM DDR3 diagnostic SW

    http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_Overview#EMIF_.28External_Memory_Interface.29

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init#Run_mtest

    http://processors.wiki.ti.com/index.php/DM816x_Design_Resources#DDR

    http://processors.wiki.ti.com/images/b/b2/DDR3-Bring-up-Overview.pdf

    http://processors.wiki.ti.com/index.php/AM389x_C6A816x_DM816x_Hardware_Design_Guide

    http://processors.wiki.ti.com/index.php/Netra_DDR3_register_initialization_tools

    pragnesh virani said:
    Or is there anyway to load u-boot to DDR through CCS?

    http://processors.wiki.ti.com/index.php/U-boot_Debug_in_CCSv5

    processors.wiki.ti.com/index.php/Sitara_Linux_Training:_uboot_linux_debug_with_ccsv5

    Regards,
    Pavel