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Interface TMS320C6678 with FPGA

joe lindula
Mastermind 6910 points
Other Parts Discussed in Thread: TMS320C6678

I want to interface my FPGA with the TMS320C6678 and want some input on the best way to interface the two devices. I've been using the TigerSharc from ADI which has an external 64-bit data bus, 32-bit address bus, chip select and read/write signals. Pretty simple interface and easy to code in the FPGA. I don't see such an interface with the TI processors. If anyone has done a design that interfaces such devices can you please share what you did?

 

Respectfully,

joe

  • 0
    TI__Mastermind 30825 points

    We've had wide EMIF interfaces on a number of our devices in the past for communicating to FPGA's, and we do have the EMIF16 (16 bit data, 32 bit address) but it may not have the performance you need.

    There are plenty of other alternatives such as SRIO, PCIe, and SGMII for high speed connections to FPGA.

    Do you have details of data rates you'd need to achieve?

    Many random suggestions can be made, but details are required to make appropriate suggestions.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Mastermind 6910 points

    Chad,

     

    Hi, is it possible to do 100-Mhz Reads and Writes on the EMIF bus?

    Respectfully,

    joe

  • 0 in reply to joe lindula
    TI__Mastermind 30825 points

    Joe,

    Can you be more specific, a frequency of reads/writes w/o data size isn't very useful.  The EMIF 16 operates at up to 133MHz but it's an Async interface, so you're not going to get 200MB/s transfer rates if that's what you're asking for.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Mastermind 6910 points

    Can I transfer 16-bits of data every 10ns? Do you know where I can find the maximum data rate that I can send/recv? I'll look at the EMIF 16 User Guide maybe it is there?

  • 0 in reply to joe lindula
    TI__Mastermind 30825 points

    It's an Asynchronous EMIF that runs at 1/SYSCLK7 (CPU/6 or 133MHz when device is at 1GHz.)  You're going to have setup and hold times that in multiples of the EMIF clock cycle.  So no, it would not be able to transfer 16-bits of data every 10ns.   You'd probably want to step to something like SGMII (1GbE Ethernet) for this.

    -Chad

  • 0 in reply to Chad Courtney
    Mastermind 6910 points

    Chad,

     

    Hi, isn't the SYSCLK7 derived from the CORECLK input pins. The data sheet has that input max at 312.5Mhz. How do you get 133Mhz?

  • 0 in reply to joe lindula
    Mastermind 6240 points

    Hi,

    The input clock can be multiplied first and then divided (fig 7.7 of datasheet), that's the way it's achieved the higher clock rates (1 and 1.25 GHZ). In the second phase the first output is divided by 6 and the 133 MHz clock is obtained.

  • 0 in reply to joe lindula
    TI__Mastermind 30825 points

    SYSCLK7 is a fixed divider coming from the main PLL's (PLLOUT - see figure 7-7 of the data manual.)  While CORECLK can be up to 312.5MHz, what's being feed to the SYSCLK7 is the PLLOUT - which is also the SYSCLK1 that goes to the C66x CorePac's.  This is set to be 1GHz for a 1GHz device.  Hence, 1GHz/6 -> 133MHz fixed for 1GHz device.

    If you're looking at the mux that shows you can feed CORECLK directly into the SYSCLK dividers, you should note that the muxes are only set such that it would come directly from CORECLK and not from the PLLOUT if the PLL is disabled, which is not the the case for normal usage.

    Best Regards,
    Chad

  • 0 in reply to Chad Courtney
    Mastermind 6910 points

    Chad,

     

    Hi, can you point to a reference design that I can look over that interfaces the DSP with an FPGA and uses the EMI16?

    thanks

    joe