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DDR3 init and write leveling on DM814x

Jean-Michel CAPITAN
Prodigy 160 points

HI,

Based on following web link : http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot, we are trying to understand values read in the associated .GEL file :

http://processors.wiki.ti.com/index.php/File:Ti814x_ddr3.zip

Question 1

The board used is the DM8148 board from Mistral, with four Micron MT41J128M8 part per memory controller (8 total 8bit memory chips).

In the MICRON datasheet, one can read that there are 14 ROW address bits : "ROW Addressing : 16K (A[13:0])

But in the GEL file, the SDRCR register is set to 0x61C011B2, with ROWSIZE set to 3h => 12 bits.

Can you please clarify this point ?

Question 2:

The .OUT application found from the link above is dedicated to software leveling, thus to determine optimal range for RD_DQS_SLAVE_RATIO, WR_DQS...

But one can read in the .GEL file some initial values specified for those registers (lines 274 to 282).

How must we configure those initial values ?

Regards,

Jean-Michel

  • 0
    Guru 31670 points

    Jean-Michel,

    You can ignore the values configured in GEL file. The values you get after running the algorithm needs to be used finally for the board. You can even edit the GEL file with these values if you want use the GEL file again for running something else, if required.