DM814x DDR3 Write Leveling

Hi,

we are designing an AM3871 Board with one 16-bit DDR3 Memory Device (Micron MT41J128M16HA-15E) connected to the DDR0 controller.
We do neither use U-Boot nor CCS and thus cannot follow the instructions in TI814x-DDR3-Init-U-Boot.
For these reasons, I want to use DDR3 Read-Write Leveling.
Unfortunately, the TRM does not explicitly describe how to do this.

In advance, I tried for testing purposes to enable Full Leveling on the DM8148 EVM. I wonder, why U-Boot for this board is using
Ratio Forced Leveling instead of Auto-Leveling, although this is recommended for DDR3 devices.

I do the following steps on the DM8148 EVM:

* DDRPHYCR:  RDEYE_LVL_DIS, GATE_LVL_DIS and WR_LVL_DIS Bits are cleared
* DATAx_REG_PHY_WRLVL_INIT_RATIO_0: Initialized with Start Values
* DATAx_REG_PHY_WRLVL_INIT_MODE_0: WRLVL_INIT_MODE_SEL Bits are set
* DATAx_REG_PHY_GATELVL_INIT_RATIO_0: Initialized with Start Values
* DATAx_REG_PHY_GATELVL_INIT_MODE_0: GATELVL_INIT_MODE_SEL Bits are set
* Initialize remaining DDR PHY and DDR Memory Controller registers
* Enabling Initialization and Refresh in SDRRCR register
> Enabling Leveling in RDWR_LVL_RMP_CTRL (RDWRLVL_EN Bit set)
> Start Full Leveling in RWLCR (RDWRLVLFULL_START Bit set)
> Check for Leveling Timeouts in SDRSTAT (-> no timeouts)

Afterwards DDR Memory Dump in the Debugger is instable. Without the steps (>) everything works fine (with the Ratio Values from U-Boot).

Is there any issue about Read/Write Leveling on this processor or am I doing something wrong? 

Any help from the TI Support Team or others is appreciated.

Thanks,

Guenther Weiss