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dm814x ddr3 sw leveling problem

richard lee2
Intellectual 490 points

We built a custom board based on dm814x with two 1gigabit ddr3 rams (with 16bits) installed in emif0.

emif1 is not used.

After run ti814x_ddr3.gel, load & run DDR3_SlaveRatio_ByteWiseSearch_TI814x.out

rd dqs, rd gate dqs, wr dqs converging failed. i tested only emif0.

I tried various seeds but failed. But, EVM board from mistral passes this test completely. all three

values are converged in one shot.

Please let me know the state of my custom board.

1. ddr3 physically inaccessible or not ? data corruption ? just a converging problem ?

power problem or schematic problem possible in this state ?

2. is there any possibility that corrupted code is executing at the core ? when i tested jtag (xds100v2)

connection, it reported data transfer failed 83%. then without crc/checksum that check the binary

integrity, core can execute corrupted code. But binary executing state looks fine, displaying console

message properly..., so i think, there must be transfer correction algorithms is kicking in.

thanks in advance.

BR.

  • 0
    Intellectual 490 points

    [CortexA8] Enter 0 for DDR Controller 0 & 1 for DDR Controller 1
    0
    DDR START ADDR=0x80000000

    Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
    a2

    Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
    34

    Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
    0
    Enter the input file Name
    aaaa
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    WR DATA RATIO MAXIMUM VALUE DIDN'T CONVERGE
    WR DATA RATIO MINIMUM VALUE DIDN'T CONVERGE
    *********************************************************
        Byte level Slave Ratio Search Program Values  
    *********************************************************
                BYTE3    BYTE2    BYTE1    BYTE0
    *********************************************************
    Read DQS MAX        0     0     35     0
    Read DQS MIN        0     0     0     0
    Read DQS OPT        0     0     1a     0
    *********************************************************
    Read DQS GATE MAX    0    0     0     a3
    Read DQS GATE MIN    0    0     0     0
    Read DQS GATE OPT    0    0     0     51
    *********************************************************
    Write DQS MAX        1     0     0     0
    Write DQS MIN       0     0     0     0
    Write DQS OPT        0     0     0     0
    *********************************************************
    Write DATA MAX        0     0     0     0
    Write DATA MIN        0     0     0     0
    Write DATA OPT        0     0     0     0
    *********************************************************
    Enter 0 for DDR Controller 0 & 1 for DDR Controller 1
    0
    DDR START ADDR=0x80000000

    Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
    51

    Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
    1a

    Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
    0
    Enter the input file Name
    aaaa
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE

  • 0 in reply to richard lee2
    Intellectual 490 points

    Following is output from 8148 EVM

    [CortexA8] Enter 0 for DDR Controller 0 & 1 for DDR Controller 1

    0

    DDR START ADDR=0x80000000

    Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window

    A2

    Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window

    34

    Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window

    0

    Enter the input file Name

    aaaa

    *********************************************************

    Byte level Slave Ratio Search Program Values

    *********************************************************

    BYTE3 BYTE2 BYTE1 BYTE0

    *********************************************************

    Read DQS MAX 67 67 6a 6a

    Read DQS MIN 5 8 7 4

    Read DQS OPT 36 37 38 37

    *********************************************************

    Read DQS GATE MAX 1b7 195 185 170

    Read DQS GATE MIN 59 4e 3b a

    Read DQS GATE OPT 108 f1 e0 bd

    *********************************************************

    Write DQS MAX 9d a2 90 8b

    Write DQS MIN 0 0 0 0

    Write DQS OPT 4e 51 48 45

    *********************************************************

    Write DATA MAX b8 b6 af b9

    Write DATA MIN 50 51 4e 51

    Write DATA OPT 84 83 7e 85

    *********************************************************

  • 0 in reply to richard lee2
    Intellectual 490 points

    i selected 400MHz frequency.

    ( script > DDR3_EMIF0_EMIF1_400MHz_Config )

    ddr3 ic is MT41J256M16-125

  • 0 in reply to richard lee2
    Intellectual 490 points

    is there anybody to help me, plz..

    just want to know what is the source of problem. power or signal ?

  • 0 in reply to richard lee2
    Guru 31670 points

    Richard,

    Have you given the trace lengths properly?

  • 0 in reply to Renjith Thomas
    Intellectual 490 points

    Renjith,

    Thanks for reply.

    because all trace is about 2", i specified in excel sheet and get result a2/34/0.

    BR.

  • 0 in reply to richard lee2
    Guru 31670 points

    Richard,

    Are you sure that the tracelengths is all 2"? Do you have the precise values?

    Also can you attach the excelsheet that youv'e used?

  • 0 in reply to Renjith Thomas
    Intellectual 490 points

    i rechecked with artwork engineer.

    data inserted to attached excel file is actual value measured.

    but with these data (8a/34/0 or 8a/34/ffffffffff, non-converge symptom continued.

    7183.RatioSeed_TI814x.xls

    BR.

    richard Lee

  • 0 in reply to richard lee2
    Guru 31670 points

    Richard,

    Can you try with invert clock == 1?

  • 0 in reply to Renjith Thomas
    Intellectual 490 points

    Renjith,

    this is result with invert clkout=1 (10a/34/7f). these parameters are not working, neither.

    can i check whether ddr3 is working or not ?

    BR.

    richard.

    ------------------------------------------------------------------

    Enter 0 for DDR Controller 0 & 1 for DDR Controller 1
    0
    DDR START ADDR=0x80000000

    Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
    10a

    Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
    34

    Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
    7f
    Enter the input file Name
    aaaaa
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
    WR DATA RATIO MAXIMUM VALUE DIDN'T CONVERGE
    WR DATA RATIO MINIMUM VALUE DIDN'T CONVERGE
    *********************************************************
        Byte level Slave Ratio Search Program Values  
    *********************************************************
                BYTE3    BYTE2    BYTE1    BYTE0
    *********************************************************
    Read DQS MAX        0     0     0     0
    Read DQS MIN        0     0     0     0
    Read DQS OPT        0     0     0     0
    *********************************************************
    Read DQS GATE MAX    0    0     0     0
    Read DQS GATE MIN    0    0     0     0
    Read DQS GATE OPT    0    0     0     0
    *********************************************************
    Write DQS MAX        0     0     0     0
    Write DQS MIN       0     0     0     0
    Write DQS OPT        0     0     0     0
    *********************************************************
    Write DATA MAX        0     0     0     0
    Write DATA MIN        0     0     0     0
    Write DATA OPT        0     0     0     0
    *********************************************************

  • 0 in reply to richard lee2
    Guru 31670 points

    RIchard,

    Will it be possible to share one the schematics of the interface? Also using CCS can you try to access any of the DDR addresses 0x8000_0000 onwards and see whether you are able to read/write to any of them?

  • 0 in reply to Renjith Thomas
    Intellectual 490 points

    I tried writing & reading from 0x8000_0000 ~ 0x8000_0028

    when writing 0xff to all, i get

    when writing 0x00 to all, i get

    something looks to be written, but it is not consistent.

    these are schematic related.

    BR

    richard.

  • 0 in reply to Renjith Thomas
    Intellectual 490 points

    To make sure, i executed ddr3_400Mhz script gel file and checked memory.

    #1 is original data -> #2 is after 0xff written -> #3 after 0x00 -> #4 after 0xff -> #5 after 0x00 ...

  • 0 in reply to richard lee2
    Guru 31670 points

    Richard,

    Have you configured all the DDR registers, SDRCR, SDRRCR, SDRTIM1-3?

  • 0 in reply to Renjith Thomas
    Intellectual 490 points

    Renjith,

    i ran DDR3_EMIF0_EMIF1_400MHz_Config() of ti814x_ddr3.gel.

    it includes initialization of such registers.

    Thanks.

    BR.

    richard.

  • 0 in reply to Renjith Thomas
    Intellectual 490 points

    This is ti814x_ddr3.gel that i used.

    3201.TI814x_ddr3.gel

    BR.

    richard.

  • 0 in reply to richard lee2
    Guru 31670 points

    Richard,

    I have gone through the GEL file. Looks like this is stock GEL file that you got for the EVM. There are few major changes that needs to be done.

    1. Since you are using on EMIF-0, you just have to initialize EMIF-0 only. You can disable EMIF-1 completely.

    2. LISA mapping is for both EMIF-0 and EMIF-1. This has to be changed and DDR interleaving needs to be removed in the LISA registers. 

    3. Timing values needs to be corrected according to your DDR device and clock selected. 

  • 0 in reply to Renjith Thomas
    Intellectual 490 points

    Renjith,

    Thanks for your reply.

    Is there any reference gel file that i can use for my case ?

    BR.

    Richard.

  • 0 in reply to richard lee2
    Guru 31670 points

    Richard,

    Unfortunately, I don't have one. 

  • 0 in reply to Renjith Thomas
    Intellectual 490 points

    Renjith,

    thanks for your help

    i finally solved problem.

    Problem arises from my pcb's poor performance. it cannot run ddr3 at 400MHz.

    When i tried 200MHz, everything was perfect.

    BR.

    Richard.