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DM814x DDR3 SW Leveling - Byte Wise

Le George
Intellectual 425 points

Tool      : CCS 5.5.0.00077
Platform  : Ubuntu 12.04
Objective : Byte wise SW leveling
Ref.      : http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot



Under CPSR, if T=1 (THUMB) the code ran automatically after being loaded and the console input option ]does not appear.
So, I've changed T=0 (ARM), but I got the error messages as shown in Run-Err.png.
The input parameters are in these order:
0
0x9C
0x34
0x9
RVR_DDR3_SW_LEVELING_OUTPUT

Are my inputs wrong?

RVR-Output - Output from the "DDR0_RegisterReadBack" hot menu.

Help please....

1423.RVR-Output.txt
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CortexA8: GEL Output: ===============================================================================================
CortexA8: GEL Output: DDR0 Controller and PHY Register Read Back
CortexA8: GEL Output: ===============================================================================================
CortexA8: GEL Output: SDRAM CONFIG (SDRCR ) Register Value is : 0x61C011B2
CortexA8: GEL Output: SDRAM CONFIG (SDRCR2 ) Register Value is : 0x00000000
CortexA8: GEL Output: SDRAM_REF_CTRL (SDRRCR ) Register Value is : 0x00000C30
CortexA8: GEL Output: SDRAM_TIM_1 (SDRTIM1 ) Register Value is : 0x0AAAD4DB
CortexA8: GEL Output: SDRAM_TIM_2 (SDRTIM2 ) Register Value is : 0x682F7FDA
CortexA8: GEL Output: SDRAM_TIM_3 (SDRTIM3 ) Register Value is : 0x501F82BF
CortexA8: GEL Output: DDR_PHY_CTRL_1 (DDRPHYCR) Register Value is : 0x00170209
CortexA8: GEL Output: SDRAM_ZQCR (ZQCR ) Register Value is : 0x50074BE1
CortexA8: GEL Output: DDR0_IO_CTRL (DDRIOCTRL) Register Value is : 0x00030303
CortexA8: GEL Output: VTP0_CTRL_REG (VTP_CNTRL) Register Value is : 0x00000067
CortexA8: GEL Output: CMD0_DLL_LOCK_DIFF Register Value is : 0x00000004
CortexA8: GEL Output: CMD1_DLL_LOCK_DIFF Register Value is : 0x00000004
CortexA8: GEL Output: CMD2_DLL_LOCK_DIFF Register Value is : 0x00000004
CortexA8: GEL Output: CMD0_INVERT_CLKOUT Register Value is : 0x00000000
CortexA8: GEL Output: CMD1_INVERT_CLKOUT Register Value is : 0x00000000
CortexA8: GEL Output: CMD2_INVERT_CLKOUT Register Value is : 0x00000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0
    TI__Guru**** 170625 points

    Hi Le George,

    Please refer to the below e2e thread:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/321922.aspx

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points

    Le George,

    The TI814x_ddr3.gel is initializing only the DDR3 memory.

    When connecting to the Cortex-A8 for first time, there is DM8148_EVM.gel file which is auto-executed on Cortex-A8 connect. This GEL file is initializing everything you need. Then you should remove this DM8148_EVM.gel and add the TI814x_ddr3.gel file, then this step "Select Script -> TI814x DDR Configuration -> DDR3_EMIF0_EMIF1_400MHz_Config"

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 425 points

    Pavel,

    1. Under the CPSR registers, should T be set to 0 (ARM)? If T=1 (THUMB), the code got automatically executed after loaded into memory and the console input prompt never appears.

    2. When CortexA8 is connected, the default GEL file (e.g. DM8148_EVM.GEL) is auto-executed, how do I verify that this action has taken place? To manually reload it and rerun the GEL initialization, what are the required initialization steps (scripts)?

    3. Sometimes, why does it take multiple loads to successfully load the *.out file with the XDS100V2 device? It normally takes one try with the USB560v2 device.

    4. The other link (Elam) that you had mentioned shows similar configuration except it includes the M3_RTOS and M3_IIS that are being used. Are they required for the auto-executed GEL when the Cortex-A8 being connected?

    5. Repeating the same test (Script initialization, Run->Load) for the same JTAG device got different results. Should the output be the same? Ditto for repeating the same test with another JTAG device.

    1738.DDR3_400MHz_USB560v2_Run3.txt
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    *********************************************************
    Byte level Slave Ratio Search Program Values
    *********************************************************
    BYTE3 BYTE2 BYTE1 BYTE0
    *********************************************************
    Read DQS MAX 0 0 0 0
    Read DQS MIN 0 0 0 0
    Read DQS OPT 0 0 0 0
    *********************************************************
    Read DQS GATE MAX 0 0 0 0
    Read DQS GATE MIN 0 0 0 0
    Read DQS GATE OPT 0 0 0 0
    *********************************************************
    Write DQS MAX 0 0 0 b
    Write DQS MIN 0 0 0 0
    Write DQS OPT 0 0 0 5
    *********************************************************
    Write DATA MAX 0 0 0 0
    Write DATA MIN 0 0 0 0
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    3276.DDR3_400MHz_XDS100V2_Run2.txt
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    *********************************************************
    Byte level Slave Ratio Search Program Values
    *********************************************************
    BYTE3 BYTE2 BYTE1 BYTE0
    *********************************************************
    Read DQS MAX 0 0 35 0
    Read DQS MIN 0 0 0 0
    Read DQS OPT 0 0 1a 0
    *********************************************************
    Read DQS GATE MAX 0 0 0 0
    Read DQS GATE MIN 0 0 0 0
    Read DQS GATE OPT 0 0 0 0
    *********************************************************
    Write DQS MAX 0 0 a 0
    Write DQS MIN 0 5 8 7
    Write DQS OPT 0 80000002 9 80000003
    *********************************************************
    Write DATA MAX 0 0 0 0
    Write DATA MIN 0 0 0 0
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    1070.DDR3_400MHz_XDS100V2_Run3.txt
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    *********************************************************
    Byte level Slave Ratio Search Program Values
    *********************************************************
    BYTE3 BYTE2 BYTE1 BYTE0
    *********************************************************
    Read DQS MAX 0 0 0 0
    Read DQS MIN 0 0 0 0
    Read DQS OPT 0 0 0 0
    *********************************************************
    Read DQS GATE MAX 0 0 0 0
    Read DQS GATE MIN 0 0 0 0
    Read DQS GATE OPT 0 0 0 0
    *********************************************************
    Write DQS MAX 0 0 0 0
    Write DQS MIN 0 0 0 0
    Write DQS OPT 0 0 0 0
    *********************************************************
    Write DATA MAX 0 0 0 0
    Write DATA MIN 0 0 0 0
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    6. Is there another quick test program to verify that DDR3 can run at different clock rate?

    Note: I've modified the Mistral DDR3 project to execute code in DDR3 (Controller 0) at clock rate 200MHz-not sure how to configure the GEL at 400MHz.

    7. We're creating a custom DM8147 board. I believe that our board does not come with the 3D-engine. Is it OK to use the GEL DM8147 or DM8148?

    8. I run "Select Script -> TI814x DDR Configuration -> DDR3_EMIF0_EMIF1_400MHz_Config" each time prior "Run->Load".

    Regards,
    G.

  • 0 in reply to Le George
    TI__Guru**** 170625 points

    George,

    Le George said:
    1. Under the CPSR registers, should T be set to 0 (ARM)? If T=1 (THUMB), the code got automatically executed after loaded into memory and the console input prompt never appears.

    The ARM mode is set by default and you should keep it. I mean there is no need to manually change this CPSR.T bit to 0 (ARM mode), as it should be by default.

    Le George said:
    2. When CortexA8 is connected, the default GEL file (e.g. DM8148_EVM.GEL) is auto-executed, how do I verify that this action has taken place? To manually reload it and rerun the GEL initialization, what are the required initialization steps (scripts)?

    Before you connect to Cortex-A8 core, you should check that the DM8148_EVM.GEL file is selected:

    Tools -> GEL files -> DM8148_EVM.GEL

    See the screen shot below:

    Make sure you have selected the Cortex-A8 core (as in the screen shot).

    Then, when connect to the Cortex-A8 core, you should see in the CCS console the below output:

    CortexA8: GEL Output:
    Connecting Target...
    CortexA8: Output:      ****  DM8148 ALL ADPLL INIT IS In Progress .........
    CortexA8: GEL Output:      A8 ADPLLJ CLKOUT  value is  = 600
    CortexA8: GEL Output:      L3  ADPLLJ CLKOUT  value is  = 200
    CortexA8: GEL Output:      DSP ADPLLJ CLKOUT  value is  = 500
    CortexA8: GEL Output:      DSS ADPLLJ CLKOUT  value is  = 200
    CortexA8: GEL Output:      HDVICP ADPLLJ CLKOUT  value is  = 266
    CortexA8: GEL Output:      SGX ADPLLJ CLKOUT  value is  = 200
    CortexA8: GEL Output:      USB ADPLLJ CLKOUT  value is  = 192
    CortexA8: GEL Output:      VIDEO-0 ADPLLJ CLKOUT  value is  = 54
    CortexA8: GEL Output:      VIDEO-1 ADPLLJ CLKOUT  value is  = 148
    CortexA8: GEL Output:      VIDEO-2/HDMI ADPLLJ CLKOUT  value is  = 148
    CortexA8: GEL Output:      AUDIO ADPLLJ CLKOUT  value is  = 200
    CortexA8: Output:      ****  DM8148 ALL ADPLL INIT IS  Done **************
    CortexA8: Output:     PRCM for C674x is in Progress, Please wait.....  
    CortexA8: GEL Output:      CP0...Done
    CortexA8: GEL Output:      CP1...Done
    CortexA8: GEL Output:      CP2...Done
    CortexA8: GEL Output:      CP3...Done
    CortexA8: GEL Output:      CP4...Done
    CortexA8: GEL Output:      CP5...Done
    CortexA8: GEL Output:      CP6...Done
    CortexA8: Output:     User Can Connect to C674x   
    CortexA8: Output:     PRCM for C674x is DONE ******  
    CortexA8: Output:     PRCM for Control Module in Progress
    CortexA8: Output:     PRCM for Control Module Done
    CortexA8: Output:     PRCM for OCMCRAM0/1 Initialization in Progress
    CortexA8: Output:     PRCM for OCMCRAM0 Initialization Done
    CortexA8: GEL Output:      ***** Configuring ethernet Clk and Mux....*****
    CortexA8: GEL Output:      ***** GMII pin mux and Clk initialized....*****
    CortexA8: Output:     PRCM for SPI-0 CS-0 is in Progress, Please wait.....  
    CortexA8: GEL Output:      ***** SPI-0 CS-0 is initialized....*****
    CortexA8: Output:     PRCM for SD/MMC0 are in Progress, Please wait.....  
    CortexA8: GEL Output:      ***** MMC0/SD is initialized....*****
    CortexA8: GEL Output:      ****  Configuring DDR PLL to 533 MHz.........
    CortexA8: GEL Output:      DDR ADPLLJ CLKOUT  value is  = 533
    CortexA8: Output:      ****  DM8148 DDR3 EVM EMIF0 and EMIF1 configuration in progress.........
    CortexA8: Output:     Busy reading back DMM registers Please wait ...
    CortexA8: Output:     DMM register read successfully  
    CortexA8: Output:      ****  DM8148 DDR3 EVM EMIF0 and EMIF1 configuration is DONE ****
    CortexA8: GEL Output: Connecting Target... Done.

    This is auto-executed, as we have the below function into the DM8148_EVM.GEL (which is auto-executed when connect to the Cortex-A8 core):

    OnTargetConnect()
    {
        GEL_TextOut( "\nConnecting Target...\n" );
     
        GEL_Reset();
        ALL_ADPLL_CLOCKS_ENABLE_API();
        C674xClkEnable_API();     
        ControlModule_ClkEnable();
        PrcmAlwayOnClkEnable();
        Ethernet_PinMux_Setup();
        SPI_Setup();
        SD_MMC0_Setup();
        DDR3_EMIF0_EMIF1_533MHz_Config();
        
        GEL_TextOut( "Connecting Target... Done.\n\n" );
    }

    If you do not have any initialization when connect to the Cortex-A8 core, you should manually add/load some fully operational GEL file (not only for DDR3) and manually start the scripts to initialize the things that are initialized from the auto-executed function (PLLs, PRCM, Control Module, etc)

    Le George said:
    3. Sometimes, why does it take multiple loads to successfully load the *.out file with the XDS100V2 device? It normally takes one try with the USB560v2 device.

    I have only Blackhawk USB560M JTAG emulator, and it always works fine from the first time. I have no view over the XDS100v2 emulator.

    Le George said:
    4. The other link (Elam) that you had mentioned shows similar configuration except it includes the M3_RTOS and M3_IIS that are being used. Are they required for the auto-executed GEL when the Cortex-A8 being connected?

    No, M3-RTOS and M3-ISS (and DSP/C674x) cores do not have any impact here. Only the Cortex-A8 core is used.

    Le George said:
    5. Repeating the same test (Script initialization, Run->Load) for the same JTAG device got different results. Should the output be the same? Ditto for repeating the same test with another JTAG device.

    I am not sure I understand what you mean here.

    Le George said:

    6. Is there another quick test program to verify that DDR3 can run at different clock rate?

    Note: I've modified the Mistral DDR3 project to execute code in DDR3 (Controller 0) at clock rate 200MHz-not sure how to configure the GEL at 400MHz.

    The TI814x_ddr3.gel file has options to test at DDR3 at 300MHz, 333MHz, 400MHz, 450MHz, 533MHz. Do you need to test the DDR3 at 200MHz?

    Le George said:
    7. We're creating a custom DM8147 board. I believe that our board does not come with the 3D-engine. Is it OK to use the GEL DM8147 or DM8148?

    Yes, DM8148 GEL should be fine. It configures the SGX PLL, but I think this should not be an issue.

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 425 points

    Pavel,

    2. DM8148_EVM.GEL

       Running this GEL prior connecting the Cortex-A8 core has little effect with our tests.
       However, we got the message below of both custom boards with most fields contains 0's:
         "... MINIMUM VALUE DIDN'T CONVERGE"
       The EVM board had no problem.

    Note: Using a different GEL file, the CONVERGE message went away for the custom board. The result is identical for 3 repeated tests with the same input data set. However, the output is the same with the TI input values. Hmmm...

    2388.DM8147_400MHz_RRGEL_Log.txt
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    [CortexA8] Enter 0 for DDR Controller 0 & 1 for DDR Controller 1
    0
    DDR START ADDR=0x80000000
    Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
    0x9c
    Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
    0x34
    Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
    0x9
    Enter the input file Name
    DM8147_400MHz_RRGEL_1
    *********************************************************
    Byte level Slave Ratio Search Program Values
    *********************************************************
    BYTE3 BYTE2 BYTE1 BYTE0
    *********************************************************
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

       Perhaps, if we could have access to the source code for DDR3_SlaveRatio_ByteWiseSearch_TI814x.out would be helpful or a different GEL file.

    5. Some output fields are different after I've retried the same test several times.

    6. 200Hz is fine. We're looking at 600MHz and 800MHz.


    Thank you so much for taking time in answering all my questions.
    Regards,
    G

  • 0 in reply to Le George
    TI__Guru**** 170625 points

    Le George,

    Le George said:
    2. DM8148_EVM.GEL

       Running this GEL prior connecting the Cortex-A8 core has little effect with our tests.

    This DM8148_EVM.gel file should be run (automatically) at the same time of connecting to the Cortex-A8 core or (manually) after connecting to the Cortex-A8 core. This DM8148_EVM.gel file should not be run (manually) prior/before connecting to the Cortex-A8 core.

    Le George said:
    6. 200Hz is fine. We're looking at 600MHz and 800MHz.

    Refer to the DM814x datasheet:

    8.13.4.2.4.1 Compatible JEDEC DDR3 Devices
    the DDR3 interface is compatible with DDR3-1600 devices
    DDR3 devices with speed grades up to DDR3-1600 are supported; however, max clock rate will still be limited to 533 MHz as stated in Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller.

    DDR2/DDR3 supports up to 533 MHz


    Table 7-4. Device Operating Points (OPPs)
    OPP166  (1.35V) - DDR at 533MHz

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/241886/847777.aspx#847777

    To sum up, DDR3 supports up to 533MHz.

    Best regards,
    Pavel

  • 0 in reply to Le George
    TI__Guru**** 170625 points

    Le George,

    Le George said:
    However, we got the message below of both custom boards with most fields contains 0's:
         "... MINIMUM VALUE DIDN'T CONVERGE"
       The EVM board had no problem.

    Please go through all the steps described in the wiki:

    http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot#Overview

    1. Calculate the seed values to be input to the slave ratio search program ie:“DDR3_SlaveRatio_ByteWiseSearch_TI814x.out” as described in the subsequent sections.
    2. Configure the DDR controller (Also referred as EMIF) with the timing parameters calculated from the spreadsheet File:DM814x DDR Controller Register Configuration spreadsheet v1.0.zip based on the timing parameters mentioned in the data sheet of the specific DDR device being used.
    3. Configure the DDR PHY slave ratio registers with the respective seed values calculated from the spreadsheet.


    See also the below links:

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init_Wordwise_SWleveling#Running_the_app

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/245226.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/247633.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/245918.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/120436.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/249408.aspx

    Regards,
    Pavel