Hello,
I am looking for information on the performance limits of the TMD320C6455 DDR2 interface in terms of arbitration of the ddr2 interface. Specifically I’m interested if there any numbers that help identify the limits of accessing the DDR2 by multiple masters. For example, if software was written such that a DMA is used to organize data residing in DDR2 and another DMA is used to move the organized data from DDR2 to the SRIO interface. In such an example, assuming that arbitration needs to manage accesses (by the EDMA) to the DDR2 during re-organization and during data movement from ddr2 to the SRIO interface, are there any numbers that might give a clue what limits exist for accessing the ddr2?
Thanks,
Jackie