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Hello,
I am looking for information on the performance limits of the TMD320C6455 DDR2 interface in terms of arbitration of the ddr2 interface. Specifically I’m interested if there any numbers that help identify the limits of accessing the DDR2 by multiple masters. For example, if software was written such that a DMA is used to organize data residing in DDR2 and another DMA is used to move the organized data from DDR2 to the SRIO interface. In such an example, assuming that arbitration needs to manage accesses (by the EDMA) to the DDR2 during re-organization and during data movement from ddr2 to the SRIO interface, are there any numbers that might give a clue what limits exist for accessing the ddr2?
Thanks,
Jackie
Jackie,
What numbers you are looking. Mainly, I am not sure which limits you are concerned about.
The best I can figure from your description is that you want to simultaneously re-organize data and also write it to an external device. And you want to figure out how to avoid errors in that race between the two operations. If that is what you are doing, then change what you are doing so you have two buffers for ping/pong so you can deal with one at a time.
If there are any performance benchmark documents, you would have found them when you searched TI.com and the Wiki already. So as an easy rule-of-thumb, you can expect to get at least 50% of the DDR's theoretical bandwidth. With a high percentage of bursting accesses, you can get much higher, but the interaction of reads and writes and different pages being accessed will probably keep you from reaching above 90%.
Regards,
RandyP
Hi guys, let me jump in here...
Sort of a theoretical quesiton...so as Randy points out you have a theoretical answer.
Are there more details on the exact use case and specific issues that might be a concern?
RandyP,
Thanks for the insight.
Jackie,
It looks like this question is still open for you. Was there something more specific you are looking for or are they any other details you can provide?
Thanks,
Clinton