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C6455 DDR2 Test Failed when timer open

Xueyang Zhu
Prodigy 70 points

I design a ddr test case, but I found that test always failed when timer open but not interrupt.

Processor: TMS320C6455BCTZA, TI
DDR2_CLK=250MHz, tDDR_CLK=4ns

DDR: MT47H128M16HG-3IT,Micron
CL=5, tCK=3ns

Test Case:
step1.Write 1KB to ddr offset [0, 0x400), then read back and compare them.
step2.Write 1KB to ddr offset [0x400, 0x800), [0x800, 0xC00),[0x1000, 0x1400),[0x2000, 0x2400),[0x4000, 0x4400),[0x8000, 0x8400)... until the end of ddr space.
step3.Read back 1KB from offset [0x400, 0x800) and compare them.
step4.Read back 1KB from offset [0x800, 0xC00) and compare them.
step5.Read back 1KB from offset [0x1000, 0x1400) and compare them.
step6.Read back 1KB from offset [0x2000, 0x2400) and compare them.
...

The above code is running in the L2 RAM，and L1D cache is open but L2 cache is disable.
I have checked ddr timing and property configuration, and I think it's correct:
SDTIM1: tRFC = 50, tRP=3, tRCD=3, tWR=3, tRAS=11, tRC=14, tRRD=3, tWTR=1,
SDTIM2: tODT=2, tSXNR=52, tSXRD=199, tRTP=1, tCKE=2
CAS latency=5, read latency=6

The test result is weird.
1. When I close all dsp timer,test case will be passed every time.

2. When I open one of dsp timer, and I disable the system interrupt:
Every time, test case run to "step4 Read back 1KB from offset [0x800, 0xC00) and compare them"，
The value read back is not what I write at "step2", and the value is seems like something in the stack.
And only ddr space offset [0x800, 0xC00) test failed, others seems ok.

I guess maybe bank switch in ddr write operation failed, then I try to modify ddr configuration and
extend some timing values, but it does not work.

So how can I explain the relationship between ddr test failed and timer open?

  • 0
    TI__Mastermind 35645 points
    Hi,

    We would work on this and will get back to you at the earliest.

    Thanks & regards,
    Sivaraj K
  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    Probably, if the timer is open, the assembler routine start_timer would start running a timer and a counter. So, the timer would be

    configured to interrupt the routine when the timer counter register (CNT) reaches count limit, the interrupt would be triggered and the program counter would jump to the vector table and then to the interrupt service routine  which closes the timer and sets a flag to exit the start_timer routine. This is obvious that, the CPU would be forced to serve the timer interrupt on a high priority and the PC would jump to the respective ISR which would reallocate the stack dynamically according to the timer ISR which would probably cause the DDR space offset collapses at step4 read back 1KB from offset (0x800, 0xC00) since it jumped to stack memory.

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Prodigy 70 points
    Thanks very much for your reply, maybe i haven't describe this problem clearly in the post.
    My code is a standalone application, not running on the bios, so, before the test, i only open the timer, but not enable the timer interrupt.
    I dont think there is any interrupt happened when my test case running. And i did another test, if i close all timer,but enable the external interrupt which is 2ms periodically, the test case will be passed, maybe it's not interrupt service routing affect the test result.
  • 0 in reply to Sivaraj Kuppuraj
    Prodigy 70 points
    Sorry to add another point, i use the timer as periodically, not single. I found test result abnormally, so i disable interrupt before test case running, and test failed again, seems timer expired still affect ddr readwrite, i remember that timer has a output pin TOUTL , but i can not close it, is that possiblely affect ?