I design a ddr test case, but I found that test always failed when timer open but not interrupt.
Processor: TMS320C6455BCTZA, TI
DDR2_CLK=250MHz, tDDR_CLK=4ns
DDR: MT47H128M16HG-3IT,Micron
CL=5, tCK=3ns
Test Case:
step1.Write 1KB to ddr offset [0, 0x400), then read back and compare them.
step2.Write 1KB to ddr offset [0x400, 0x800), [0x800, 0xC00),[0x1000, 0x1400),[0x2000, 0x2400),[0x4000, 0x4400),[0x8000, 0x8400)... until the end of ddr space.
step3.Read back 1KB from offset [0x400, 0x800) and compare them.
step4.Read back 1KB from offset [0x800, 0xC00) and compare them.
step5.Read back 1KB from offset [0x1000, 0x1400) and compare them.
step6.Read back 1KB from offset [0x2000, 0x2400) and compare them.
...
The above code is running in the L2 RAM，and L1D cache is open but L2 cache is disable.
I have checked ddr timing and property configuration, and I think it's correct:
SDTIM1: tRFC = 50, tRP=3, tRCD=3, tWR=3, tRAS=11, tRC=14, tRRD=3, tWTR=1,
SDTIM2: tODT=2, tSXNR=52, tSXRD=199, tRTP=1, tCKE=2
CAS latency=5, read latency=6
The test result is weird.
1. When I close all dsp timer,test case will be passed every time.
2. When I open one of dsp timer, and I disable the system interrupt:
Every time, test case run to "step4 Read back 1KB from offset [0x800, 0xC00) and compare them"，
The value read back is not what I write at "step2", and the value is seems like something in the stack.
And only ddr space offset [0x800, 0xC00) test failed, others seems ok.
I guess maybe bank switch in ddr write operation failed, then I try to modify ddr configuration and
extend some timing values, but it does not work.
So how can I explain the relationship between ddr test failed and timer open?
