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Configuring termination on C6657 DDR3 controller

Weichun Yuan
Expert 1210 points

We are trying to configure C6657 DDR3 controller with MT41J128M8 DDR3 chip based on spreadsheet in TI document sprabl2a. We always see some bit errors. During debug, we found that DQS from DDR to DSP DDR3 controller shows some sign of impedance mismatch (please reference the attached scope capture).

We tried to tweak sdramcfg.ddrTerm, sdramcfg.SDRAMDrive as well as  sdramcfg.dynODT, but none of those changes makes much difference for the DQS waveform.

We also tried PDK_C6657_1_1_4 platform library on TMSDEVM6657L EVM board and saw similar DQS waveform.

From TI document SPRUGV8c, we found the following registers, as listed below, which might be relevant.

1. From the document, we could not determine if they are applicable for the DDR3 chip termination or termination on the DSP DDR3 controller. Could you please clarify that?

2. Are there other controls we can tweak for the DQS signal?

List of potential relevant registers.

1) sdcfg.SDRAM_DRIVE: SDRAM drive strength                      we understand this as drive strength from DDR3 chip. Is this correct?

2) sdcfg.DYN_OPT: Dynamic On-Die Termination.                    does this refer to DDR3 chip or DDR3 controller within DSP?

3) sdcfg.DDR_TERM: defines termination resistor value          does this refer to DDR3 chip or DDR3 controller within DSP?

4) ddr_phy_ctrl_1.IDLE_LOCAL_ODT: program controller termination during idle cycles             we understand that this refers to DDR3 controller within DSP. Is this correct? Are 0 and 1 the only values for these two bits?

5) ddr_phy_ctrl_1.WR_LOCAL_ODT: program controller termination during write cycles             we understand that this refers to DDR3 controller within DSP. Is this correct? Are 0 and 1 the only values for these two bits?

6) ddr_phy_ctrl_1.READ_LOCAL_ODT: program controller termination during read cycles             we understand that this refers to DDR3 controller within DSP. Is this correct? Are 0 and 1 the only values for these two bits?

thanks

Weichun