This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[DM8168] Video Display Latency

Other Parts Discussed in Thread: TVP5158

DM Champ,

I'm working with a customer who's using 2x DM816x for encode, transport and display.  This application will be used for robotic control so glass to glass latency is critical.  The following latency measurements have been very helpful in determining the expected latency that will be seen in the end system.  All the capture, encode, decode latencis are appealing except for the final Scale/Chroma Con. Display Delay T7–T5 This time is roughly double the capture and encode latency.  Can you kindly explain the reason (break down) for this large latency.  Is there a way to bypass/accelerate this time?

DM8168 Latency Measurements:
  • Here's some additional information.

    Experimental setup We created a small H264 elementary stream with 3 light frames and 50 dark frames.  The first light frame is an I frame, and the first dark frame is an I frame.  We then take this file and keep looping it, feeding it into the decoder.

    We send a character out the console for each I frame (or approximately 2 characters per second).  This way we can see on the scope that a frame has been submitted to the decoder.

    Attached to our display is a photo diode so we can see when the display transitions from dark to light and vice versa.  These can be viewed on a scope with the character from the console.

    We see pretty consistent numbers doing this.  There maybe a few millisecond of jitter, but not much.

    Would I be correct to assume that this is without Subframes? Yes there are no subframes in the stream.  We submit a whole frame at the time to the decoder.

    Does this include the ethernet transport delay? No there is no Ethernet delay in these numbers.  We submit frames after the Ethernet stack and we do it as fast as the decoder will let us.

    Do you know what the subsystem individual latencies are and how have you measured the latency? No yet using this method, but we are expecting the decoder to take about 15ms, and the scaler another 17ms based on work we have already done.  This means the rest of the time is being consumed somewhere else.  We are assuming this is in the HDVPSS but there may be other things in the stock decoder demo we are using.

    What operating parameters have you changed? We change the format to expect 60FPS

    Have you tried this with 1080p30? Overall latency was worse at 30 FPS.

    We ran another test where we starved the input to the decoder.  We ran the display at 60FPS, but I shoved in images to the decoder at only 30FPS.  When I did this, the latency from the decoder to the display changed from 212ms to a range of 80-105ms with quite a bit of jitter.

    If we take the Decoder at 15ms, and the scaler 4:2:0 -> 4:2:2 at 17ms then we get the a range of 48 - 73ms for the display portion.  This would imply the hardware imposes a 3 frame latency on all images being submitted for display.  Does this make sense?

     Basically we are seeing numbers that look worse than the SDK even after subtracting off the full network delay.

  • Michael

    First of all, thanks for gathering and sharing all these data

    Are you using OMX Non tunnel way of data communication? What is the A8 load?  If you use NT and A8 load s high it can affect the latency number very badly

    Normally, each processing block takes ~16ms incase of 1080p60.  There is an exception with display where it need priming of 3 frames before starting the display, so the worst case it can introduce 3-4 frame delay, which is ~48-64ms

    For example, let us look into the encode path delay. Capture + DEi + encode = 16+16+16 = 48ms (excluding the delay introduced by NT path)

    In the second display path you can avoid the scalar if you use the latest HDVPSS driver. For this you need to use the 420 path display driver, i guess VFDC do not support this driver. But if 420SP path display driver is integrated with VFDC, then you can avoid SC and that reduces ~16ms

    A few other points to reduce the NT path delay

    1. make SR0 non-cached - To avoid a lot of cache invalidation APIs
    2. make bits stream (i guess SR1) region cached
    3. Reduce the messageQ size from 1K (i think this is set as default) to 256 bytes.  This will reduce the message copy time


    Are they ready to evaluate these usecase with RDK? RDK has better data communication path compared with EZSDK SNT.  Also has support to use 420 path display driver and a few techniques to reduce the overall display latency


    regards, shiju



  • shiju,

    Thank you for posting the info.  The latency numbers we are seeing are on the RDK.  Let me clarify our setup.

    We are using the 3.5 RDK on the 8168 Spectrum digital EVM.

    We are using an HDMI interface to display data.

    We have our own H264 clip we inject into the decoder.

    The A8 is lightly loaded.

    We believe the decoder and scaler are taking about 30ms to run per image.

    The total delay from the decoder to the display is about 90ms. 

    This means after the decoder and scaler the total delay before we see the image on the screen is 60ms.  It is this delay we are trying to understand.  We don't know where this time going?

    Can you tell us why there is this delay?

    What can we do to improve this delay?

    With regards to your response above, what does NT refer to?

    Oliver

  • Shiju,

    I forgot to mention we are using the standard Decode example program provided with the RDK.  We have modified this to inject our video clip into the decoder.  We do this from RAM to avoid latency issues with reading from disk.

    Oliver

  • Shiju,

    Looking at the demo code, I see an area that might be causing the delay.  In demo_vdec_vdis_frames_send.c there appears to be a function VdecVdis_ipcFramesStart where we call

        VdecVdis_ipcFramesInitFrameObj(gVdecVdis_config.ipcFrames.frameObj,
                                       MCFW_IPCFRAMES_MAX_NUM_ALLOC_FRAMES,
                                       &chInfoList);
    The MCFW_IPCFRAMES_MAX_NUM_ALLOC_FRAMES is currently set to 4.  Is there a reason why this number would be set to 4 instead of 1?

    Oliver

  • Can you share the h264 elementary stream you are using.. We would like to try it on a UDwroks DVR setup and measure the latency. We have hooks in place to measure latency at each component. The demo needs minor modification to set the walltime. We can measure upto the point driver gives frame to HDVPSS h/w display. We don't have the means to check when it exactly gets displayed on TV

  • Badri,

    Thank you for your offer of assistance.  Please find the attached clip which is approximately 60 frames.  The first 3 frames are very light in color, and the next 53 frames are very dark.

    Oliver

    dark_N_frames.h264.zip
  • Thank you for sharing the stream.How many channels of decode do you want me to try out for latency measurement purpose. Is it single channel ?

  • Oliver

    I have mistaken you use OMX SDK framework from TI and this is because of the keyword "OMX" in the post header.  NT means Non-tunnel communication, used in OMX context. 

    Good that you use RDK, which is far better in terms of feature-set and latency

    The RDK chain for this particular usecase is

    ipcBitsOut(HLOS) (16ms) -> ipcBitsIn (Vid-M3) (16ms)  -> DEC link (33ms) -> MPSCLR Link (no delay if resolution is <= HD) -> SWMS Link (33ms) -> Display Link (3*16 ms)

    = 16+16+33+0+33+48 = ~150ms

    ipcBits links are configured as noNotifyMode mode which could add 16 + 16 ms (worst case) delay in the pipeline.  We can avoid this 32ms by enabling the notify mode

    As Badri mentioned we will measure the latency with your stream and get back to you 


    Regards, shiju

  • Shiju/Badri,

    Thanks for your help so far and sorry for the misnomer in the title. We are only decoding a single stream of video.

    How would the latency scale if multiple streams were decoded and potentially mosaiced? 

    So just to verify my understanding, if we were to set the ipcBits to noNotifyMode then we could essentially eliminate the ipcBitsOut(HLOS) (16ms) -> ipcBitsIn (Vid-M3) (16ms) latencies.

    Is there anyway to reduce the Display Link latency? And can you breifly explain the 3x16ms? Does that have to do with the frame pipeline being three frames deep?

  • >> How would the latency scale if multiple streams were decoded and potentially mosaiced? 

    Normally each IP in DM8168 can do 2ch 1080p30 decode or scale in real time.  So if you are not overloading the IP, then the max latency will be 33ms, it can be smaller if you do only say one channel SD


    >> Is there anyway to reduce the Display Link latency? And can you breifly explain the 3x16ms? Does that have to do with the frame pipeline being three frames deep?

    This is not possible as it is a HW + driver limitation.  The display queue has a minimum depth of  3 and it required to start the display only after prime 3 buffers/frames.   So even a frame is available in the input side of the display it will be dsiplayed only after 3 display interrupts


    regards, shiju

     

  • Below is the statistics with the clip you shared. This is for one channel 1080P60. The clip has only 56 frames and I don't see any light frame followed by dark frame. Anyhow the content doesn't matter for the latency calculation below

    [m3vpss ]
     [m3vpss ]  *** [MP_SCLR0 ] Statistics ***
     [m3vpss ]
     [m3vpss ]  Total Frames Received  : 2720
     [m3vpss ]  Total Frames Forwarded : 2720
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]  CH  | In Recv In Reject Processed  Latency(DRV) Processed  Rejected
     [m3vpss ]  Num | FPS     FPS       FPS        Min / Max    Frames     Frames
     [m3vpss ]  -------------------------------------------------------------------
     [m3vpss ]
     [m3vpss ]  *** [SWMS0] Mosaic Statistics ***
     [m3vpss ]
     [m3vpss ]  Elasped Time: 34 secs
     [m3vpss ]
     [m3vpss ]  Output Request FPS   : 60 fps (2066 frames)
     [m3vpss ]  Output Actual  FPS   : 60 fps (2066 frames)
     [m3vpss ]  Output Drop    FPS   : 0 fps (0 frames)
     [m3vpss ]  Output Reject  FPS   : 0 fps (0 frames)
     [m3vpss ]  Scaling Internal     : 16 ms
     [m3vpss ]  Scaling Internal min : 16 ms
     [m3vpss ]  Scaling Internal max : 17 ms
     [m3vpss ]
     [m3vpss ]  Win | Window Repeat Drop Recv Que  FID Invlid Acc Event          Invalid   Que Reject Reject Latency   OutBufCopy InBufCopy
     [m3vpss ]  Num | FPS    FPS    FPS  FPS  FPS  FPS        Count (Max/Min)    CH Frames Frames     Frames Min / Max FPS        FPS
     [m3vpss ]  ---------------------------------------------------------------------------------------------------------------------------
     [m3vpss ]    0 |     60      0    0    0   60          0        0 (  0/255)         0          0      0  35 /  40          0         0
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]  *** [SWMS0] Mosaic Parameters ***
     [m3vpss ]
     [m3vpss ]  Output FPS: 60
     [m3vpss ]
     [m3vpss ]  Win | Ch  | Input      | Input          | Input         | Input       | Output     |  Output         | Output        | Output      | Low Cost | SWMS | Data  | Blank |
     [m3vpss ]  Num | Num | Start X, Y | Width x Height | Pitch Y / C   | Memory Type | Start X, Y |  Width x Height | Pitch Y / C   | Memory Type | ON / OFF | Inst | Format| Frame |
     [m3vpss ]  ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
     [m3vpss ]    0 |   0 |    0,    0 |  1920 x   1080 | 16384 / 32768 | TILED       |    0,    0 |  1920 x   1080 |  3840 /      0 | NON-TILED   |      OFF |    0 |  420SP |   OFF |
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]  *** [SWMS1] Mosaic Statistics ***
     [m3vpss ]
     [m3vpss ]  Elasped Time: 34 secs
     [m3vpss ]
     [m3vpss ]  Output Request FPS   : 60 fps (2066 frames)
     [m3vpss ]  Output Actual  FPS   : 60 fps (2066 frames)
     [m3vpss ]  Output Drop    FPS   : 0 fps (0 frames)
     [m3vpss ]  Output Reject  FPS   : 0 fps (0 frames)
     [m3vpss ]  Scaling Internal     : 16 ms
     [m3vpss ]  Scaling Internal min : 16 ms
     [m3vpss ]  Scaling Internal max : 17 ms
     [m3vpss ]
     [m3vpss ]  Win | Window Repeat Drop Recv Que  FID Invlid Acc Event          Invalid   Que Reject Reject Latency   OutBufCopy InBufCopy
     [m3vpss ]  Num | FPS    FPS    FPS  FPS  FPS  FPS        Count (Max/Min)    CH Frames Frames     Frames Min / Max FPS        FPS
     [m3vpss ]  ---------------------------------------------------------------------------------------------------------------------------
     [m3vpss ]    0 |     60      0    0    0   60          0        0 (  0/255)         0          0      0  35 /  41          0         0
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]  *** [SWMS1] Mosaic Parameters ***
     [m3vpss ]
     [m3vpss ]  Output FPS: 60
     [m3vpss ]
     [m3vpss ]  Win | Ch  | Input      | Input          | Input         | Input       | Output     |  Output         | Output        | Output      | Low Cost | SWMS | Data  | Blank |
     [m3vpss ]  Num | Num | Start X, Y | Width x Height | Pitch Y / C   | Memory Type | Start X, Y |  Width x Height | Pitch Y / C   | Memory Type | ON / OFF | Inst | Format| Frame |
     [m3vpss ]  ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
     [m3vpss ]    0 |   0 |    0,    0 |  1920 x   1080 | 16384 / 32768 | TILED       |    0,    0 |  1920 x   1080 |  3840 /      0 | NON-TILED   |      OFF |    0 |  420SP |   OFF |
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]  3725213: DISPLAY: HDDAC(BP0) : 59 fps, Latency (Min / Max) = ( 50 / 51 ), Callback Interval (Min / Max) = ( 16 / 17 ) DropCount:0 DispLatency (Min / Max) = ( 33 / 42 ) !!!
     [m3vpss ]  3725213: DISPLAY DRV: HDDAC(BP0) : Q:[2801] Display:[2811], Repeat:[11], DQ:[2799]
     [m3vpss ]  3725213: DISPLAY: UNDERFLOW COUNT: HDMI(BP0) 2066, HDDAC(BP0) 2066, DVO2(BP1) 2066, SDDAC(SEC1) 4133
     [m3vpss ]  3725213: SYSTEM  : FREE SPACE : System Heap      = 67320 B, Mbx = 10239 msgs)
     [m3vpss ]  3725213: SYSTEM  : FREE SPACE : SR0 Heap         = 16831744 B (16 MB)
     [m3vpss ]  3725213: SYSTEM  : FREE SPACE : Frame Buffer     = 599780224 B (571 MB)
     [m3vpss ]  3725213: SYSTEM  : FREE SPACE : Bitstream Buffer = 289430400 B (276 MB)
     [m3vpss ] TILER_STATS: CNT :8BIT
     [m3vpss ] TILER_STATS: CNT RESOLUTION:    16384 x 8192
     [m3vpss ] TILER_STATS: BUCKET RESOLUTION: 2048 x 1662
     [m3vpss ] TILER_STATS: NUM FREE BUCKETS:  37
     [m3vpss ] TILER_STATS: NUM USED BUCKETS:  3
     [m3vpss ] TILER_STATS: TOTAL FREE AREA:   126959616 (94 %)
     [m3vpss ] TILER_STATS: TOTAL USED AREA:   7225344 (5 %)
     [m3vpss ] TILER_STATS: TOTAL WASTE AREA:  0 (0 %)
     [m3vpss ] TILER_STATS: MAX WIDTH RECT:    2048 x 456
     [m3vpss ] TILER_STATS: MAX HEIGHT RECT:    2048 x 456
     [m3vpss ] TILER_STATS: RES ALLOC COUNT [1080P] :  3
     [m3vpss ] TILER_STATS: CNT :16BIT
     [m3vpss ] TILER_STATS: CNT RESOLUTION:    32768 x 4096
     [m3vpss ] TILER_STATS: BUCKET RESOLUTION: 2048 x 832
     [m3vpss ] TILER_STATS: NUM FREE BUCKETS:  77
     [m3vpss ] TILER_STATS: NUM USED BUCKETS:  3
     [m3vpss ] TILER_STATS: TOTAL FREE AREA:   130605056 (97 %)
     [m3vpss ] TILER_STATS: TOTAL USED AREA:   3612672 (2 %)
     [m3vpss ] TILER_STATS: TOTAL WASTE AREA:  0 (0 %)
     [m3vpss ] TILER_STATS: MAX WIDTH RECT:    2048 x 228
     [m3vpss ] TILER_STATS: MAX HEIGHT RECT:    2048 x 228
     [m3vpss ] TILER_STATS: RES ALLOC COUNT [1080P] :  3
     [m3vpss ]  3725216: SYSTEM  : FREE SPACE : Tiler 8-bit      = 126959616 B (121 MB)  - TILER ON
     [m3vpss ]  3725216: SYSTEM  : FREE SPACE : Tiler 16-bit     = 130605056 B (124 MB)  - TILER ON
     [m3vpss ]  3725216: DISPLAY: DVO2(BP1)  : 59 fps, Latency (Min / Max) = ( 50 / 50 ), Callback Interval (Min / Max) = ( 16 / 17 ) DropCount:0 DispLatency (Min / Max) = ( 36 / 42 ) !!!
     [m3vpss ]  3725217: DISPLAY DRV: DVO2(BP1)  : Q:[2802] Display:[2808], Repeat:[7], DQ:[2800]
     [m3video]      3731217: HDVICP-ID:0
     [m3video] All percentage figures are based off totalElapsedTime
     [m3video]               totalAcquire2wait :0 %
     [m3video]               totalWait2Isr :52 %
     [m3video]               totalIsr2Done :0 %
     [m3video]               totalWait2Done :52 %
     [m3video]               totalDone2Release :0 %
     [m3video]               totalAcquire2Release :54 %
     [m3video]               totalAcq2acqDelay :45 %
     [m3video]               totalElapsedTime in msec :   51358
     [m3video]               numAccessCnt:    3081
     [m3video]              IVA-FPS :      60
     [m3video]              Average time spent per frame in microsec:    8667
     [m3video]      3731218: HDVICP-ID:1
     [m3video] All percentage figures are based off totalElapsedTime
     [m3video]               totalAcquire2wait :0 %
     [m3video]               totalWait2Isr :0 %
     [m3video]               totalIsr2Done :0 %
     [m3video]               totalWait2Done :0 %
     [m3video]               totalDone2Release :0 %
     [m3video]               totalAcquire2Release :0 %
     [m3video]               totalAcq2acqDelay :0 %
     [m3video]               totalElapsedTime in msec :       0
     [m3video]               numAccessCnt:       0
     [m3video]              IVA-FPS :       0
     [m3video]              Average time spent per frame in microsec:       0
     [m3video]      3731218: HDVICP-ID:2
     [m3video] All percentage figures are based off totalElapsedTime
     [m3video]               totalAcquire2wait :0 %
     [m3video]               totalWait2Isr :0 %
     [m3video]               totalIsr2Done :0 %
     [m3video]               totalWait2Done :0 %
     [m3video]               totalDone2Release :0 %
     [m3video]               totalAcquire2Release :0 %
     [m3video]               totalAcq2acqDelay :0 %
     [m3video]               totalElapsedTime in msec :       0
     [m3video]               numAccessCnt:       0
     [m3video]              IVA-FPS :       0
     [m3video]              Average time spent per frame in microsec:       0
     [m3video]
     [m3video]  *** DECODE Statistics ***
     [m3video]
     [m3video]  Elasped Time           : 34 secs
     [m3video]
     [m3video]
     [m3video]  CH  | In Recv In User  Out
     [m3video]  Num | FPS     Skip FPS FPS
     [m3video]  -----------------------------------
     [m3video]    0 |      60        0  60
     [m3video]
     [m3video] Multi Channel Decode Average Submit Batch Size
     [m3video] Max Submit Batch Size : 24
     [m3video] IVAHD_0 Average Batch Size : 1
     [m3video] IVAHD_0 Max achieved Batch Size : 1
     [m3video] IVAHD_1 Average Batch Size : 0
     [m3video] IVAHD_1 Max achieved Batch Size : 0
     [m3video] IVAHD_2 Average Batch Size : 0
     [m3video] IVAHD_2 Max achieved Batch Size : 0
     [m3video]
     [m3video] Multi Channel Decode Batch break Stats
     [m3video] Total Number of Batches created: 2066
     [m3video] All numbers are based off total number of Batches created
     [m3video]       Batch breaks due to batch sizeexceeding limit: 100 %
     [m3video]       Batch breaks due to ReqObj Que being empty: 0 %
     [m3video]       Batch breaks due to changed resolution class: 0 %
     [m3video]       Batch breaks due to interlace and progressivecontent mix: 0 %
     [m3video]       Batch breaks due to channel repeat: 0 %
     [m3video]       Batch breaks due to different codec: 0 %
     [m3video] Total Number of Batches created: 0
     [m3video] All numbers are based off total number of Batches created
     [m3video]       Batch breaks due to batch sizeexceeding limit: 0 %
     [m3video]       Batch breaks due to ReqObj Que being empty: 0 %
     [m3video]       Batch breaks due to changed resolution class: 0 %
     [m3video]       Batch breaks due to interlace and progressivecontent mix: 0 %
     [m3video]       Batch breaks due to channel repeat: 0 %
     [m3video]       Batch breaks due to different codec: 0 %
     [m3video] Total Number of Batches created: 0
     [m3video] All numbers are based off total number of Batches created
     [m3video]       Batch breaks due to batch sizeexceeding limit: 0 %
     [m3video]       Batch breaks due to ReqObj Que being empty: 0 %
     [m3video]       Batch breaks due to changed resolution class: 0 %
     [m3video]       Batch breaks due to interlace and progressivecontent mix: 0 %
     [m3video]       Batch breaks due to channel repeat: 0 %
     [m3video]       Batch breaks due to different codec: 0 %
     [m3video]
     [m3vpss ]
     [m3vpss ]  3734222: LOAD: CPU: 7.8% HWI: 2.2%, SWI:1.0%
     [m3vpss ]
     [m3vpss ]  3734222: LOAD: TSK: IPC_IN_M30          : 0.3%
     [m3vpss ]  3734222: LOAD: TSK: DISPLAY0            : 0.5%
     [m3vpss ]  3734222: LOAD: TSK: DISPLAY1            : 0.3%
     [m3vpss ]  3734222: LOAD: TSK: DUP0                : 0.2%
     [m3vpss ]  3734222: LOAD: TSK: SWMS0               : 1.2%
     [m3vpss ]  3734223: LOAD: TSK: SWMS1               : 1.2%
     [m3vpss ]  3734223: LOAD: TSK: MP_SCLR_FWD_Q0      : 0.2%
     [m3vpss ]  3734223: LOAD: TSK: MISC                : 0.7%
     [m3vpss ]
     [m3video]
     [m3video]  3734724: LOAD: CPU: 5.0% HWI: 0.7%, SWI:0.5%
     [m3video]
     [m3video]  3734724: LOAD: TSK: IPC_OUT_M30         : 0.7%
     [m3video]  3734724: LOAD: TSK: IPC_BITS_IN0        : 0.3%
     [m3video]  3734724: LOAD: TSK: DEC0                : 1.2%
     [m3video]  3734724: LOAD: TSK: DEC_PROCESS_TSK_0   : 1.2%
     [m3video]  3734724: LOAD: TSK: MISC                : 0.4%
     [m3video]
     [c6xdsp ]
     [c6xdsp ]  3732311: LOAD: CPU: 0.2% HWI: 0.0%, SWI:0.0%
     [c6xdsp ]
     [c6xdsp ]  3732311: LOAD: TSK: MISC                : 0.2%
     [c6xdsp ]

     =============
     Run-Time Menu
     =============

     1: Capture Settings
     2: Encode  Settings
     3: Decode  Settings
     4: Display Settings
     5: Audio Capture <TVP5158> & Encode <AAC-LC, G711> demo
     6: Change Playback Channel <valid only if capture/playback is active>
     7: Audio encode demo <File In/Out>
     8: Audio decode demo <File In/Out>

     i: Print detailed system information
     s: Core Status: Active/In-active
     f: Switch IVA Channel Map

     e: Stop Demo

     Enter Choice: i


     [m3vpss ]
     [m3vpss ]  *** [MP_SCLR0 ] Statistics ***
     [m3vpss ]
     [m3vpss ]  Total Frames Received  : 4687
     [m3vpss ]  Total Frames Forwarded : 4687
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]  CH  | In Recv In Reject Processed  Latency(DRV) Processed  Rejected
     [m3vpss ]  Num | FPS     FPS       FPS        Min / Max    Frames     Frames
     [m3vpss ]  -------------------------------------------------------------------
     [m3vpss ]
     [m3vpss ]  *** [SWMS0] Mosaic Statistics ***
     [m3vpss ]
     [m3vpss ]  Elasped Time: 32 secs
     [m3vpss ]
     [m3vpss ]  Output Request FPS   : 61 fps (1967 frames)
     [m3vpss ]  Output Actual  FPS   : 61 fps (1967 frames)
     [m3vpss ]  Output Drop    FPS   : 0 fps (0 frames)
     [m3vpss ]  Output Reject  FPS   : 0 fps (0 frames)
     [m3vpss ]  Scaling Internal     : 16 ms
     [m3vpss ]  Scaling Internal min : 16 ms
     [m3vpss ]  Scaling Internal max : 17 ms
     [m3vpss ]
     [m3vpss ]  Win | Window Repeat Drop Recv Que  FID Invlid Acc Event          Invalid   Que Reject Reject Latency   OutBufCopy InBufCopy
     [m3vpss ]  Num | FPS    FPS    FPS  FPS  FPS  FPS        Count (Max/Min)    CH Frames Frames     Frames Min / Max FPS        FPS
     [m3vpss ]  ---------------------------------------------------------------------------------------------------------------------------
     [m3vpss ]    0 |     61      0    0    0   61          0        0 (  0/255)         0          0      0  35 /  40          0         0
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]  *** [SWMS0] Mosaic Parameters ***
     [m3vpss ]
     [m3vpss ]  Output FPS: 60
     [m3vpss ]
     [m3vpss ]  Win | Ch  | Input      | Input          | Input         | Input       | Output     |  Output         | Output        | Output      | Low Cost | SWMS | Data  | Blank |
     [m3vpss ]  Num | Num | Start X, Y | Width x Height | Pitch Y / C   | Memory Type | Start X, Y |  Width x Height | Pitch Y / C   | Memory Type | ON / OFF | Inst | Format| Frame |
     [m3vpss ]  ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
     [m3vpss ]    0 |   0 |    0,    0 |  1920 x   1080 | 16384 / 32768 | TILED       |    0,    0 |  1920 x   1080 |  3840 /      0 | NON-TILED   |      OFF |    0 |  420SP |   OFF |
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]  *** [SWMS1] Mosaic Statistics ***
     [m3vpss ]
     [m3vpss ]  Elasped Time: 32 secs
     [m3vpss ]
     [m3vpss ]  Output Request FPS   : 61 fps (1967 frames)
     [m3vpss ]  Output Actual  FPS   : 61 fps (1967 frames)
     [m3vpss ]  Output Drop    FPS   : 0 fps (0 frames)
     [m3vpss ]  Output Reject  FPS   : 0 fps (0 frames)
     [m3vpss ]  Scaling Internal     : 16 ms
     [m3vpss ]  Scaling Internal min : 16 ms
     [m3vpss ]  Scaling Internal max : 17 ms
     [m3vpss ]
     [m3vpss ]  Win | Window Repeat Drop Recv Que  FID Invlid Acc Event          Invalid   Que Reject Reject Latency   OutBufCopy InBufCopy
     [m3vpss ]  Num | FPS    FPS    FPS  FPS  FPS  FPS        Count (Max/Min)    CH Frames Frames     Frames Min / Max FPS        FPS
     [m3vpss ]  ---------------------------------------------------------------------------------------------------------------------------
     [m3vpss ]    0 |     61      0    0    0   61          0        0 (  0/255)         0          0      0  35 /  41          0         0
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]  *** [SWMS1] Mosaic Parameters ***
     [m3vpss ]
     [m3vpss ]  Output FPS: 60
     [m3vpss ]
     [m3vpss ]  Win | Ch  | Input      | Input          | Input         | Input       | Output     |  Output         | Output        | Output      | Low Cost | SWMS | Data  | Blank |
     [m3vpss ]  Num | Num | Start X, Y | Width x Height | Pitch Y / C   | Memory Type | Start X, Y |  Width x Height | Pitch Y / C   | Memory Type | ON / OFF | Inst | Format| Frame |
     [m3vpss ]  ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
     [m3vpss ]    0 |   0 |    0,    0 |  1920 x   1080 | 16384 / 32768 | TILED       |    0,    0 |  1920 x   1080 |  3840 /      0 | NON-TILED   |      OFF |    0 |  420SP |   OFF |
     [m3vpss ]
     [m3vpss ]
     [m3vpss ]  3757994: DISPLAY: HDDAC(BP0) : 59 fps, Latency (Min / Max) = ( 50 / 52 ), Callback Interval (Min / Max) = ( 16 / 17 ) DropCount:0 DispLatency (Min / Max) = ( 41 / 42 ) !!!
     [m3vpss ]  3757994: DISPLAY DRV: HDDAC(BP0) : Q:[4768] Display:[4778], Repeat:[11], DQ:[4766]
     [m3vpss ]  3757995: DISPLAY: UNDERFLOW COUNT: HDMI(BP0) 1967, HDDAC(BP0) 1967, DVO2(BP1) 1967, SDDAC(SEC1) 3934
     [m3vpss ]  3757995: SYSTEM  : FREE SPACE : System Heap      = 67320 B, Mbx = 10238 msgs)
     [m3vpss ]  3757995: SYSTEM  : FREE SPACE : SR0 Heap         = 16831744 B (16 MB)
     [m3vpss ]  3757995: SYSTEM  : FREE SPACE : Frame Buffer     = 599780224 B (571 MB)
     [m3vpss ]  3757995: SYSTEM  : FREE SPACE : Bitstream Buffer = 289430400 B (276 MB)
     [m3vpss ] TILER_STATS: CNT :8BIT
     [m3vpss ] TILER_STATS: CNT RESOLUTION:    16384 x 8192
     [m3vpss ] TILER_STATS: BUCKET RESOLUTION: 2048 x 1662
     [m3vpss ] TILER_STATS: NUM FREE BUCKETS:  37
     [m3vpss ] TILER_STATS: NUM USED BUCKETS:  3
     [m3vpss ] TILER_STATS: TOTAL FREE AREA:   126959616 (94 %)
     [m3vpss ] TILER_STATS: TOTAL USED AREA:   7225344 (5 %)
     [m3vpss ] TILER_STATS: TOTAL WASTE AREA:  0 (0 %)
     [m3vpss ] TILER_STATS: MAX WIDTH RECT:    2048 x 456
     [m3vpss ] TILER_STATS: MAX HEIGHT RECT:    2048 x 456
     [m3vpss ] TILER_STATS: RES ALLOC COUNT [1080P] :  3
     [m3vpss ] TILER_STATS: CNT :16BIT
     [m3vpss ] TILER_STATS: CNT RESOLUTION:    32768 x 4096
     [m3vpss ] TILER_STATS: BUCKET RESOLUTION: 2048 x 832
     [m3vpss ] TILER_STATS: NUM FREE BUCKETS:  77
     [m3vpss ] TILER_STATS: NUM USED BUCKETS:  3
     [m3vpss ] TILER_STATS: TOTAL FREE AREA:   130605056 (97 %)
     [m3vpss ] TILER_STATS: TOTAL USED AREA:   3612672 (2 %)
     [m3vpss ] TILER_STATS: TOTAL WASTE AREA:  0 (0 %)
     [m3vpss ] TILER_STATS: MAX WIDTH RECT:    2048 x 228
     [m3vpss ] TILER_STATS: MAX HEIGHT RECT:    2048 x 228
     [m3vpss ] TILER_STATS: RES ALLOC COUNT [1080P] :  3
     [m3vpss ]  3757997: SYSTEM  : FREE SPACE : Tiler 8-bit      = 126959616 B (121 MB)  - TILER ON
     [m3vpss ]  3757997: SYSTEM  : FREE SPACE : Tiler 16-bit     = 130605056 B (124 MB)  - TILER ON
     [m3vpss ]  3757999: DISPLAY: DVO2(BP1)  : 59 fps, Latency (Min / Max) = ( 50 / 50 ), Callback Interval (Min / Max) = ( 16 / 17 ) DropCount:0 DispLatency (Min / Max) = ( 41 / 42 ) !!!
     [m3vpss ]  3757999: DISPLAY DRV: DVO2(BP1)  : Q:[4769] Display:[4775], Repeat:[7], DQ:[4767]
     [m3video]      3763999: HDVICP-ID:0
     [m3video] All percentage figures are based off totalElapsedTime
     [m3video]               totalAcquire2wait :0 %
     [m3video]               totalWait2Isr :52 %
     [m3video]               totalIsr2Done :0 %
     [m3video]               totalWait2Done :52 %
     [m3video]               totalDone2Release :0 %
     [m3video]               totalAcquire2Release :54 %
     [m3video]               totalAcq2acqDelay :45 %
     [m3video]               totalElapsedTime in msec :   84141
     [m3video]               numAccessCnt:    5048
     [m3video]              IVA-FPS :      60
     [m3video]              Average time spent per frame in microsec:    8667
     [m3video]      3764000: HDVICP-ID:1
     [m3video] All percentage figures are based off totalElapsedTime
     [m3video]               totalAcquire2wait :0 %
     [m3video]               totalWait2Isr :0 %
     [m3video]               totalIsr2Done :0 %
     [m3video]               totalWait2Done :0 %
     [m3video]               totalDone2Release :0 %
     [m3video]               totalAcquire2Release :0 %
     [m3video]               totalAcq2acqDelay :0 %
     [m3video]               totalElapsedTime in msec :       0
     [m3video]               numAccessCnt:       0
     [m3video]              IVA-FPS :       0
     [m3video]              Average time spent per frame in microsec:       0
     [m3video]      3764000: HDVICP-ID:2
     [m3video] All percentage figures are based off totalElapsedTime
     [m3video]               totalAcquire2wait :0 %
     [m3video]               totalWait2Isr :0 %
     [m3video]               totalIsr2Done :0 %
     [m3video]               totalWait2Done :0 %
     [m3video]               totalDone2Release :0 %
     [m3video]               totalAcquire2Release :0 %
     [m3video]               totalAcq2acqDelay :0 %
     [m3video]               totalElapsedTime in msec :       0
     [m3video]               numAccessCnt:       0
     [m3video]              IVA-FPS :       0
     [m3video]              Average time spent per frame in microsec:       0
     [m3video]
     [m3video]  *** DECODE Statistics ***
     [m3video]
     [m3video]  Elasped Time           : 32 secs
     [m3video]
     [m3video]
     [m3video]  CH  | In Recv In User  Out
     [m3video]  Num | FPS     Skip FPS FPS
     [m3video]  -----------------------------------
     [m3video]    0 |      61        0  61
     [m3video]
     [m3video] Multi Channel Decode Average Submit Batch Size
     [m3video] Max Submit Batch Size : 24
     [m3video] IVAHD_0 Average Batch Size : 1
     [m3video] IVAHD_0 Max achieved Batch Size : 1
     [m3video] IVAHD_1 Average Batch Size : 0
     [m3video] IVAHD_1 Max achieved Batch Size : 0
     [m3video] IVAHD_2 Average Batch Size : 0
     [m3video] IVAHD_2 Max achieved Batch Size : 0
     [m3video]
     [m3video] Multi Channel Decode Batch break Stats
     [m3video] Total Number of Batches created: 1967
     [m3video] All numbers are based off total number of Batches created
     [m3video]       Batch breaks due to batch sizeexceeding limit: 100 %
     [m3video]       Batch breaks due to ReqObj Que being empty: 0 %
     [m3video]       Batch breaks due to changed resolution class: 0 %
     [m3video]       Batch breaks due to interlace and progressivecontent mix: 0 %
     [m3video]       Batch breaks due to channel repeat: 0 %
     [m3video]       Batch breaks due to different codec: 0 %
     [m3video] Total Number of Batches created: 0
     [m3video] All numbers are based off total number of Batches created
     [m3video]       Batch breaks due to batch sizeexceeding limit: 0 %
     [m3video]       Batch breaks due to ReqObj Que being empty: 0 %
     [m3video]       Batch breaks due to changed resolution class: 0 %
     [m3video]       Batch breaks due to interlace and progressivecontent mix: 0 %
     [m3video]       Batch breaks due to channel repeat: 0 %
     [m3video]       Batch breaks due to different codec: 0 %
     [m3video] Total Number of Batches created: 0
     [m3video] All numbers are based off total number of Batches created
     [m3video]       Batch breaks due to batch sizeexceeding limit: 0 %
     [m3video]       Batch breaks due to ReqObj Que being empty: 0 %
     [m3video]       Batch breaks due to changed resolution class: 0 %
     [m3video]       Batch breaks due to interlace and progressivecontent mix: 0 %
     [m3video]       Batch breaks due to channel repeat: 0 %
     [m3video]       Batch breaks due to different codec: 0 %
     [m3video]
     [m3vpss ]
     [m3vpss ]  3767004: LOAD: CPU: 7.8% HWI: 2.2%, SWI:1.0%
     [m3vpss ]
     [m3vpss ]  3767004: LOAD: TSK: IPC_IN_M30          : 0.3%
     [m3vpss ]  3767004: LOAD: TSK: DISPLAY0            : 0.5%
     [m3vpss ]  3767004: LOAD: TSK: DISPLAY1            : 0.3%
     [m3vpss ]  3767005: LOAD: TSK: DUP0                : 0.2%
     [m3vpss ]  3767005: LOAD: TSK: SWMS0               : 1.2%
     [m3vpss ]  3767005: LOAD: TSK: SWMS1               : 1.2%
     [m3vpss ]  3767005: LOAD: TSK: MP_SCLR_FWD_Q0      : 0.2%
     [m3vpss ]  3767005: LOAD: TSK: MISC                : 0.7%
     [m3vpss ]
     [m3video]
     [m3video]  3767506: LOAD: CPU: 5.0% HWI: 0.7%, SWI:0.5%
     [m3video]
     [m3video]  3767506: LOAD: TSK: IPC_OUT_M30         : 0.6%
     [m3video]  3767506: LOAD: TSK: IPC_BITS_IN0        : 0.3%
     [m3video]  3767506: LOAD: TSK: DEC0                : 1.2%
     [m3video]  3767506: LOAD: TSK: DEC_PROCESS_TSK_0   : 1.2%
     [m3video]  3767506: LOAD: TSK: MISC                : 0.5%
     [m3video]
     [c6xdsp ]
     [c6xdsp ]  3765092: LOAD: CPU: 0.2% HWI: 0.0%, SWI:0.0%
     [c6xdsp ]
     [c6xdsp ]  3765092: LOAD: TSK: MISC                : 0.2%

     

    I have highlighted the items of interest in bold.

    As you can see from the stats latency from app sending the frame to SwMs outputting the composited frame is  (min/max) (35 /  41 )

    Latency from SwmS outputting the frame to display freeing the frame after display is 50 ms.

     

    So this means effective total latency from when frame is sent to when frame starts display is:

    Min = 35 + 50 - 16 = 69 ms

    Max = 41 + 50 - 16 = 75 ms.

    There is potential to reduce the latency further by 16 ms if you don't use SwMs and instead use scaler if you don't require composited view. This is because swms will operate at periodic intervals to enable composition from multiple windows which is not the case with scaler.

    This stream is of low complexity so the decode processing time is very less as you can see in the stats 8667 usec avg to decode a frame. This could increase by 8msec for more complex streams.

    Attached is the patch with list of all changes done to RDK so that you can try the same at your end. I am not sure if patch will apply cleanly on RDK 3.5 as it is based on latest codebase.I can anyway explain the changes in the patch if you require to replicate the setup at your end.

    0131.Decode_display_latency_reduction.patch.txt
    diff --git a/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis_bits_rd.c b/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis_bits_rd.c
    index afd3854..def1a21 100755
    --- a/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis_bits_rd.c
    +++ b/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis_bits_rd.c
    @@ -95,6 +95,7 @@ static void VdecVdis_bitsRdFillEmptyBuf(VCODEC_BITSBUF_S *pEmptyBuf)
     }
     
     #define VDEC_VDIS_FRAME_DURATION_MS (33)
    +UInt64 Avsync_getWallTime();
     
     static Void VdecVdis_setFrameTimeStamp(VCODEC_BITSBUF_S *pEmptyBuf)
     {
    @@ -102,6 +103,7 @@ static Void VdecVdis_setFrameTimeStamp(VCODEC_BITSBUF_S *pEmptyBuf)
           gVdecVdis_config.frameCnt[pEmptyBuf->chnId] * VDEC_VDIS_FRAME_DURATION_MS;
         pEmptyBuf->lowerTimeStamp = (UInt32)(curTimeStamp & 0xFFFFFFFF);
         pEmptyBuf->upperTimeStamp = (UInt32)((curTimeStamp >> 32)& 0xFFFFFFFF);
    +    pEmptyBuf->timestamp = Avsync_getWallTime();
         if (0 == gVdecVdis_config.frameCnt[pEmptyBuf->chnId])
         {
             UInt32 displayChId;
    @@ -148,7 +150,7 @@ static Void *VdecVdis_bitsRdSendFxn(Void * prm)
         OSA_semWait(&gVdecVdis_obj.thrStartSem,OSA_TIMEOUT_FOREVER);
         while (FALSE == gVdecVdis_obj.thrExit)
         {
    -        OSA_waitMsecs(MCFW_IPCBITS_SENDFXN_PERIOD_MS);
    +        OSA_waitMsecs(1);
     
             for (i = 0; i < gVdecVdis_config.numChannels; i++)
             {
    diff --git a/mcfw/src_linux/mcfw_api/ti_vdis.c b/mcfw/src_linux/mcfw_api/ti_vdis.c
    index af5e6a0..a0e0f61 100755
    --- a/mcfw/src_linux/mcfw_api/ti_vdis.c
    +++ b/mcfw/src_linux/mcfw_api/ti_vdis.c
    @@ -801,7 +801,7 @@ Int32 Vdis_setMosaicParamsDefault(VDIS_DEV vdDevId, VDIS_MOSAIC_S *psVdMosaicPar
         /* Assign mosaic layout number and number of windows */
         vdisLayoutPrm.numWin = psVdMosaicParam->numberOfWindows;
         vdisLayoutPrm.onlyCh2WinMapChanged = psVdMosaicParam->onlyCh2WinMapChanged;
    -    vdisLayoutPrm.outputFPS = psVdMosaicParam->outputFPS;
    +    vdisLayoutPrm.outputFPS = 60;
     
         /* Assign each windows coordinates, size and mapping */
         for(winId=0; winId<vdisLayoutPrm.numWin; winId++)
    diff --git a/mcfw/src_linux/mcfw_api/usecases/ti81xx/multich_vdec_vdis.c b/mcfw/src_linux/mcfw_api/usecases/ti81xx/multich_vdec_vdis.c
    index 75e1b46..1549e7a 100755
    --- a/mcfw/src_linux/mcfw_api/usecases/ti81xx/multich_vdec_vdis.c
    +++ b/mcfw/src_linux/mcfw_api/usecases/ti81xx/multich_vdec_vdis.c
    @@ -219,7 +219,7 @@ Void mulich_vdec_vdis_set_avsync_vidque_prm(Avsync_SynchConfigParams *queCfg,
             &&
             (gVsysModuleContext.vsysConfig.enableAVsync))
         {
    -        queCfg->avsyncEnable = TRUE;
    +        queCfg->avsyncEnable = FALSE;
         }
         else
         {
    @@ -399,9 +399,9 @@ Void MultiCh_createVdecVdis()
         }
     
         ipcBitsOutHostPrm.baseCreateParams.outQueParams[0].nextLink= gVdecModuleContext.ipcBitsInRTOSId;
    -    ipcBitsOutHostPrm.baseCreateParams.notifyNextLink       = FALSE;
    +    ipcBitsOutHostPrm.baseCreateParams.notifyNextLink       = TRUE;
         ipcBitsOutHostPrm.baseCreateParams.notifyPrevLink       = FALSE;
    -    ipcBitsOutHostPrm.baseCreateParams.noNotifyMode         = TRUE;
    +    ipcBitsOutHostPrm.baseCreateParams.noNotifyMode         = FALSE;
         ipcBitsOutHostPrm.baseCreateParams.numOutQue            = 1;
         ipcBitsOutHostPrm.inQueInfo.numCh                       = gVdecModuleContext.vdecConfig.numChn;
     
    @@ -430,16 +430,16 @@ Void MultiCh_createVdecVdis()
             ipcBitsOutHostPrm.chMaxReqBufSize[i] = 
                     (ipcBitsOutHostPrm.inQueInfo.chInfo[i].width * ipcBitsOutHostPrm.inQueInfo.chInfo[i].height); 
             ipcBitsOutHostPrm.totalBitStreamBufferSize [i] = 
    -                (ipcBitsOutHostPrm.chMaxReqBufSize[i] * BIT_BUF_LENGTH_LIMIT_FACTOR_HD);
    +                (ipcBitsOutHostPrm.chMaxReqBufSize[i] * 1);
     
         }
     
         ipcBitsInVideoPrm.baseCreateParams.inQueParams.prevLinkId    = gVdecModuleContext.ipcBitsOutHLOSId;
         ipcBitsInVideoPrm.baseCreateParams.inQueParams.prevLinkQueId = 0;
         ipcBitsInVideoPrm.baseCreateParams.outQueParams[0].nextLink  = gVdecModuleContext.decId;
    -    ipcBitsInVideoPrm.baseCreateParams.noNotifyMode              = TRUE;
    +    ipcBitsInVideoPrm.baseCreateParams.noNotifyMode              = FALSE;
         ipcBitsInVideoPrm.baseCreateParams.notifyNextLink            = TRUE;
    -    ipcBitsInVideoPrm.baseCreateParams.notifyPrevLink            = FALSE;
    +    ipcBitsInVideoPrm.baseCreateParams.notifyPrevLink            = TRUE;
         ipcBitsInVideoPrm.baseCreateParams.numOutQue                 = 1;
     
         for (i=0; i<ipcBitsOutHostPrm.inQueInfo.numCh; i++)
    @@ -452,7 +452,7 @@ Void MultiCh_createVdecVdis()
                 decPrm.chCreateParams[i].format                 = IVIDEO_MJPEG;
     
             decPrm.chCreateParams[i].numBufPerCh
    -                         = gVdecModuleContext.vdecConfig.decChannelParams[i].numBufPerCh;
    +                         = 3;
             decPrm.chCreateParams[i].profile                = IH264VDEC_PROFILE_ANY;
             decPrm.chCreateParams[i].displayDelay
                              = gVdecModuleContext.vdecConfig.decChannelParams[i].displayDelay;
    @@ -639,10 +639,12 @@ Void MultiCh_createVdecVdis()
             swMsPrm[i].enableLayoutGridDraw = gVdisModuleContext.vdisConfig.enableLayoutGridDraw;
     
             MultiCh_swMsGetDefaultLayoutPrm(vdDevId, &swMsPrm[i], FALSE);    /* both from 0-16 chnl */
    +        swMsPrm[i].layoutPrm.outputFPS = 60;
     
             displayPrm[i].inQueParams[0].prevLinkId    = gVdisModuleContext.swMsId[i];
             displayPrm[i].inQueParams[0].prevLinkQueId = 0;
             displayPrm[i].displayRes                = swMsPrm[i].initOutRes;
    +        displayPrm[i].queueInISRFlag = TRUE;
             if (i == 1)
     #if defined(TI_814X_BUILD) || defined(TI_8107_BUILD)
                             displayPrm[i].displayRes            = gVdisModuleContext.vdisConfig.deviceParams[VDIS_DEV_SD].resolution;
    

     

  • Badri and Shiju

    Thank you for the timing info.  Yes we know this is an easy to decode stream.  We expect to use subframes in the final version.

    After some digging, I think the code that is creating the framebuffers might be here

    static int ti81xxfb_create_framebuffers(struct ti81xxfb_device *fbdev)
    {
        int i, r;

        fbdev->num_fbs = 0;
        TFBDBG("create %d fbs\n", CONFIG_FB_TI81XX_NUM_FBS);

        /* allocate fb_info */
        for (i = 0; i < CONFIG_FB_TI81XX_NUM_FBS; i++) {

    Where CONFIG_FB_TI81XX_NUM_FBS is set to 3.  Do you know if this is where the hold up is?

    You mention the 3 frame buffers is a hard / driver limitation.  Does anyone know if this path can be shortened and if so what are the consequences of doing this?

    Oliver

  • I see in the HDVPSS UserGuide that

    FVID2 Start

    This API is used by the application to start the display operation. This is a blocking call and returns after starting the display operation. Before starting the display operation, the application has to prime at least 1 buffer with the driver using queue API. When driver is openned under VPS_GRPX_NON_FRAME_BUFFER_MODE, typically 3 buffers are used - 1 used by application and 2 buffers are queued with the driver at any given time. When driver is openned under VPS_GRPX_FRAME_BUFFER_MODE, typically 1 buffer is used.

    Would it help latency if we opened the buffer in VPS_GRPX_FRAME_BUFFER_MODE?

    Oliver

  • I don't understand the question.Are you measuring latency for the video pipeline or graphics pipeline.FBDEV is for graphics .The priming buffer length for FBDEV has no impact on video display latency and vice-versa.

  • Badri,

    We are interested in Video pipeline latency, not graphics.  Sorry for the confusion.  We are trying to figure out why there is a 3 buffer delay.  The 48ms delay that this imposes is painful.  I assume this is something on the M3?

    Oliver

  • The three buffer for display is minimum .You need 2 buffers ( Ping-Pong) so that on display interrupt the next frame begins display without underrun. A third buffer is required because frames are queued to display driver in a separate thread. The three buffer delay can be reduced to two buffers if display frames are queued in the display ISR instead of the thread context. This is what is done in RDK as you can see in the logs I shared where the display latency is ~ 33ms (2 frames @ 60 fps). Further reduction in  display latency is not possible  per my understanding. I will ask the HDVPSS driver expert to confirm on this thread.

  • Badri

    Thanks for getting back to me.  I may have misunderstood this line

     [m3vpss ]  3725213: DISPLAY: HDDAC(BP0) : 59 fps, Latency (Min / Max) = ( 50 / 51 ), Callback Interval (Min / Max) = ( 16 / 17 ) DropCount:0 DispLatency (Min / Max) = ( 33 / 42 ) !!!

    I saw this meant the total latency for the display step was 50/51 ms?  Are you saying it was 33/42?

    Oliver

  • As I explained in the previous post 50/51 is the latency measure at the point where the display has completed  display of frame and frees the frame back to previous component. This means frame started display one VSYNC previously which means display latency is 50 - 16 ~ 34 ms.

  • Hi,

     

    The minimum latency that we could achieve by queueing/dequeueing from the ISR, is two frame time, ie 33/34 ms for 60fps. Here latency is difference betwee Dequeue and queue operation. Buffer actually starts getting displayed after 16ms.

     

    Regards,

    Brijesh Jadav

  • Badri Narayanan said:

    Attached is the patch with list of all changes done to RDK so that you can try the same at your end. I am not sure if patch will apply cleanly on RDK 3.5 as it is based on latest codebase.I can anyway explain the changes in the patch if you require to replicate the setup at your end.

    0131.Decode_display_latency_reduction.patch.txt
    diff --git a/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis_bits_rd.c b/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis_bits_rd.c
    index afd3854..def1a21 100755
    --- a/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis_bits_rd.c
    +++ b/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis_bits_rd.c
    @@ -95,6 +95,7 @@ static void VdecVdis_bitsRdFillEmptyBuf(VCODEC_BITSBUF_S *pEmptyBuf)
     }
     
     #define VDEC_VDIS_FRAME_DURATION_MS (33)
    +UInt64 Avsync_getWallTime();
     
     static Void VdecVdis_setFrameTimeStamp(VCODEC_BITSBUF_S *pEmptyBuf)
     {
    @@ -102,6 +103,7 @@ static Void VdecVdis_setFrameTimeStamp(VCODEC_BITSBUF_S *pEmptyBuf)
           gVdecVdis_config.frameCnt[pEmptyBuf->chnId] * VDEC_VDIS_FRAME_DURATION_MS;
         pEmptyBuf->lowerTimeStamp = (UInt32)(curTimeStamp & 0xFFFFFFFF);
         pEmptyBuf->upperTimeStamp = (UInt32)((curTimeStamp >> 32)& 0xFFFFFFFF);
    +    pEmptyBuf->timestamp = Avsync_getWallTime();
         if (0 == gVdecVdis_config.frameCnt[pEmptyBuf->chnId])
         {
             UInt32 displayChId;
    @@ -148,7 +150,7 @@ static Void *VdecVdis_bitsRdSendFxn(Void * prm)
         OSA_semWait(&gVdecVdis_obj.thrStartSem,OSA_TIMEOUT_FOREVER);
         while (FALSE == gVdecVdis_obj.thrExit)
         {
    -        OSA_waitMsecs(MCFW_IPCBITS_SENDFXN_PERIOD_MS);
    +        OSA_waitMsecs(1);
     
             for (i = 0; i < gVdecVdis_config.numChannels; i++)
             {
    diff --git a/mcfw/src_linux/mcfw_api/ti_vdis.c b/mcfw/src_linux/mcfw_api/ti_vdis.c
    index af5e6a0..a0e0f61 100755
    --- a/mcfw/src_linux/mcfw_api/ti_vdis.c
    +++ b/mcfw/src_linux/mcfw_api/ti_vdis.c
    @@ -801,7 +801,7 @@ Int32 Vdis_setMosaicParamsDefault(VDIS_DEV vdDevId, VDIS_MOSAIC_S *psVdMosaicPar
         /* Assign mosaic layout number and number of windows */
         vdisLayoutPrm.numWin = psVdMosaicParam->numberOfWindows;
         vdisLayoutPrm.onlyCh2WinMapChanged = psVdMosaicParam->onlyCh2WinMapChanged;
    -    vdisLayoutPrm.outputFPS = psVdMosaicParam->outputFPS;
    +    vdisLayoutPrm.outputFPS = 60;
     
         /* Assign each windows coordinates, size and mapping */
         for(winId=0; winId<vdisLayoutPrm.numWin; winId++)
    diff --git a/mcfw/src_linux/mcfw_api/usecases/ti81xx/multich_vdec_vdis.c b/mcfw/src_linux/mcfw_api/usecases/ti81xx/multich_vdec_vdis.c
    index 75e1b46..1549e7a 100755
    --- a/mcfw/src_linux/mcfw_api/usecases/ti81xx/multich_vdec_vdis.c
    +++ b/mcfw/src_linux/mcfw_api/usecases/ti81xx/multich_vdec_vdis.c
    @@ -219,7 +219,7 @@ Void mulich_vdec_vdis_set_avsync_vidque_prm(Avsync_SynchConfigParams *queCfg,
             &&
             (gVsysModuleContext.vsysConfig.enableAVsync))
         {
    -        queCfg->avsyncEnable = TRUE;
    +        queCfg->avsyncEnable = FALSE;
         }
         else
         {
    @@ -399,9 +399,9 @@ Void MultiCh_createVdecVdis()
         }
     
         ipcBitsOutHostPrm.baseCreateParams.outQueParams[0].nextLink= gVdecModuleContext.ipcBitsInRTOSId;
    -    ipcBitsOutHostPrm.baseCreateParams.notifyNextLink       = FALSE;
    +    ipcBitsOutHostPrm.baseCreateParams.notifyNextLink       = TRUE;
         ipcBitsOutHostPrm.baseCreateParams.notifyPrevLink       = FALSE;
    -    ipcBitsOutHostPrm.baseCreateParams.noNotifyMode         = TRUE;
    +    ipcBitsOutHostPrm.baseCreateParams.noNotifyMode         = FALSE;
         ipcBitsOutHostPrm.baseCreateParams.numOutQue            = 1;
         ipcBitsOutHostPrm.inQueInfo.numCh                       = gVdecModuleContext.vdecConfig.numChn;
     
    @@ -430,16 +430,16 @@ Void MultiCh_createVdecVdis()
             ipcBitsOutHostPrm.chMaxReqBufSize[i] = 
                     (ipcBitsOutHostPrm.inQueInfo.chInfo[i].width * ipcBitsOutHostPrm.inQueInfo.chInfo[i].height); 
             ipcBitsOutHostPrm.totalBitStreamBufferSize [i] = 
    -                (ipcBitsOutHostPrm.chMaxReqBufSize[i] * BIT_BUF_LENGTH_LIMIT_FACTOR_HD);
    +                (ipcBitsOutHostPrm.chMaxReqBufSize[i] * 1);
     
         }
     
         ipcBitsInVideoPrm.baseCreateParams.inQueParams.prevLinkId    = gVdecModuleContext.ipcBitsOutHLOSId;
         ipcBitsInVideoPrm.baseCreateParams.inQueParams.prevLinkQueId = 0;
         ipcBitsInVideoPrm.baseCreateParams.outQueParams[0].nextLink  = gVdecModuleContext.decId;
    -    ipcBitsInVideoPrm.baseCreateParams.noNotifyMode              = TRUE;
    +    ipcBitsInVideoPrm.baseCreateParams.noNotifyMode              = FALSE;
         ipcBitsInVideoPrm.baseCreateParams.notifyNextLink            = TRUE;
    -    ipcBitsInVideoPrm.baseCreateParams.notifyPrevLink            = FALSE;
    +    ipcBitsInVideoPrm.baseCreateParams.notifyPrevLink            = TRUE;
         ipcBitsInVideoPrm.baseCreateParams.numOutQue                 = 1;
     
         for (i=0; i<ipcBitsOutHostPrm.inQueInfo.numCh; i++)
    @@ -452,7 +452,7 @@ Void MultiCh_createVdecVdis()
                 decPrm.chCreateParams[i].format                 = IVIDEO_MJPEG;
     
             decPrm.chCreateParams[i].numBufPerCh
    -                         = gVdecModuleContext.vdecConfig.decChannelParams[i].numBufPerCh;
    +                         = 3;
             decPrm.chCreateParams[i].profile                = IH264VDEC_PROFILE_ANY;
             decPrm.chCreateParams[i].displayDelay
                              = gVdecModuleContext.vdecConfig.decChannelParams[i].displayDelay;
    @@ -639,10 +639,12 @@ Void MultiCh_createVdecVdis()
             swMsPrm[i].enableLayoutGridDraw = gVdisModuleContext.vdisConfig.enableLayoutGridDraw;
     
             MultiCh_swMsGetDefaultLayoutPrm(vdDevId, &swMsPrm[i], FALSE);    /* both from 0-16 chnl */
    +        swMsPrm[i].layoutPrm.outputFPS = 60;
     
             displayPrm[i].inQueParams[0].prevLinkId    = gVdisModuleContext.swMsId[i];
             displayPrm[i].inQueParams[0].prevLinkQueId = 0;
             displayPrm[i].displayRes                = swMsPrm[i].initOutRes;
    +        displayPrm[i].queueInISRFlag = TRUE;
             if (i == 1)
     #if defined(TI_814X_BUILD) || defined(TI_8107_BUILD)
                             displayPrm[i].displayRes            = gVdisModuleContext.vdisConfig.deviceParams[VDIS_DEV_SD].resolution;
    

    Brijesh Jadav said:

    The minimum latency that we could achieve by queueing/dequeueing from the ISR, is two frame time, ie 33/34 ms for 60fps. Here latency is difference betwee Dequeue and queue operation. Buffer actually starts getting displayed after 16ms.

    Hi Badri, Brijesh

    I'm working with Oliver on this project and currently focused on integrating the patch you linked. It looks like the patch includes the queueing/dequeueing from ISRs as Brijesh mentioned. However, there appears to be no mechanism for this in the RDK version we get from UD Works (DVRRDK_03.50.00.05).

    In particular, this line does not integrate anywhere into our code: file mcfw/src_linux/mcfw_api/usecases/ti81xx/multich_vdec_vdis.c

       displayPrm[i].displayRes = swMsPrm[i].initOutRes;
    +  displayPrm[i].queueInISRFlag = TRUE;
       if (i == 1)

    Presumably, the mechanism does exist in the code somewhere, but is simply not exposed as nicely as this flag. I'm having trouble pinpointing the ISR capable of queueing/dequeueing. Could I ask either of you to help me out with this please? This would be in the M3 code somewhere?

    Thanks,
    Philipp 

  • Pls attach

    /dvr_rdk/mcfw/src_bios6/links_m3vpss/display folder

    and

    /dvr_rdk/mcfw/interfaces/link_api/displayLink.h

    from your codebase. I will merge in the changes .

  • Thank you very much Badri.

    Attached are my display/ folder and displayLink.h:

    mcfw/src_bios6/links_m3vpss/display/
    mcfw/src_bios6/links_m3vpss/display/displayLink_tsk.c
    mcfw/src_bios6/links_m3vpss/display/displayLink_priv.h
    mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c
    mcfw/interfaces/link_api/displayLink.h

    pschrader_dvr_rdk_display.zip
  • Attached are the files with latest display link changes merged in

    0576.pschrader_dvr_rdk_display.zip

  • Thanks Badri, I'll take a look.

  • Excellent, so with both your change sets (patch and DisplayLink update) I can see a 20ms improvement at 30fps. Thank you very much for your help Badri!

    Shiju Sivasankaran said:

    The RDK chain for this particular usecase is

    ipcBitsOut(HLOS) (16ms) -> ipcBitsIn (Vid-M3) (16ms)  -> DEC link (33ms) -> MPSCLR Link (no delay if resolution is <= HD) -> SWMS Link (33ms) -> Display Link (3*16 ms)

    = 16+16+33+0+33+48 = ~150ms

    I am now looking into bypassing and/or disabling the SWMS link to get rid of those 33ms. Would you have any suggestions there? Otherwise I'll have a better idea later today or Monday on what I need clarification.

    Thanks again!

    Philipp

  • So I've been trying to make modifications to the link setup in mcfw/src_linux/mcfw_api/usecases/multich_vdec_vdis.c to bypass the mosaic entirely. I've attached a patch of my changes relative to RDK v3.5 + the earlier uploaded patch.

    The patch tries to link the DUP link directly to the DISPLAY link.

    I think I'm missing something subtle as during the display link setup, there's an assertion failure:
     [m3vpss ]  23306: DISPLAY: Create in progress !!!
     [m3vpss ]  23307: Assertion @ Line: 943 in links_m3vpss/display/displayLink_drv.c: status == FVID2_SOK : failed !!!

    where status = FVID2_EINVALID_PARAMS  (i.e. -3). So somewhere I'm setting up invalid parameters.
    Any ideas on what I'm missing?

    Thanks,
    Philipp

  • Philipp

    As you know decoder always output 420 format.  At present diplsy link is configured with

    displayId = DISPLAY_LINK_DISPLAY_AUTO_SELECT

    this will auto slect BP0 and BP1 path for both the HD dsiplays.  This mode support only for input format 422, and normally SWMS do this data format conversion

    when you bypass SWMS make sure you use the dsiplay link configured as below

     for fisrt HD display

    displayPrm[i].displayId = DISPLAY_LINK_DISPLAY_SC1

    for second HD dsiplay

    displayPrm[i].displayId = DISPLAY_LINK_DISPLAY_SC2

    please note that in this case, you will not be able to show the mosic display, only single channel disply is supported

    regards, shiju

  • Ah yes, that makes sense.

    I will change the formats and get back to you.

    Thanks Shiju!

  • I managed to do the following things (slightly contrary to what you suggested, Shiju):

    1) I kept the displayLink hooked to BP0 and BP1, configured the MP-SCLR to do the 420 -> 422 conversion for me

    2) I kept the displayLink hooked to BP0 and BP1, configured the regular scaler to do the 420 -> 422 conversion for me

    3) Hooked the displayLink to SC1 and SC2, as suggested by Shiju

    Options 1) and 2) seemed to work quite well. Unfortunately, cutting out the mosaicer and using the scalers only did _not_ noticeably reduce the response time: I gained roughly 2ms. There's still some profiling I'd like to do to see how much time the scaler is taking up.

    Option 3) gives me a run-time assertion failure with a NULL handle. I haven't looked into this one yet, but I'm guessing that SC1 and SC2 require additional configuration that is not part of the default vdec+vdis demo application.

    So a question:

    a) I've tried hacking the displayLink to simply accept 420 frames and use those. I haven't had any success as of yet. Is this at all doable?

    Again, I haven't investigated the configurations for SC1 and SC2 yet, so that's what I'll do tomorrow. Are there examples of this already?

    Thanks,

    Philipp

  • Philipp

    We do have an example for 420 path display in 4ch D1 DVR - usecase file - multich_progressive_4d1_vcap_venc_vdec_vdis.c

    Please refer this


    regards, shiju


  • I found three files that relate to your suggestion:

    a) ./mcfw/src_linux/mcfw_api/usecases/ti810x/multich_progressive_4d1_vcap_venc_vdec_vdis.c
    b) ./mcfw/src_linux/mcfw_api/usecases/ti814x/multich_progressive_4d1_vcap_venc_vdec_vdis.c
    c) ./mcfw/src_linux/mcfw_api/usecases/ti816x/multich_progressive_vcap_venc_vdec_vdis.c

    All three of them seem to pass the frames through swMs (mosaicer) before going to the display link. From what I understand the mosaicer converts all incoming frames into a 422 format regardless of their original type. Is that correct?

    I think I need to sit down again and think about what exactly it is that I want to achieve here.

  • SwMs supports output in both 420SP and 422I format. THe usecase ./mcfw/src_linux/mcfw_api/usecases/ti810x/multich_progressive_4d1_vcap_venc_vdec_vdis.c is the one Shiju is referring to.

    Can you share the Vsys_printDetailedStatistics ("I" command output) logs after taking in all the patches I shared previously when playback is in progress and the log from application start of the Display Link create failure case.PLs collect Vsys_printDetailedStatistics logs couple of times with atleast 10 sec interval

  • Hi Badri,

    Thanks for your response, I will take a look at the example. Though ultimately I would like to remove the mosaicer from the chain.

    I've attached a zip of the logs. Here's a quick overview:

    Folder contents
    ---------------

    drwxr-xr-x 2 user user 4096 2013-04-09 14:09 no-swms-bp0-bp1/
    drwxr-xr-x 2 user user 4096 2013-04-09 14:08 no-swms-sc1-sc2/
    drwxr-xr-x 2 user user 4096 2013-04-09 14:17 with-swms/
    -rw-r--r-- 1 user user    0 2013-04-09 14:19 OVERVIEW.txt


    Folder "no-swms-bp0-bp1"
    ------------------------

    This folder contains the log from "./run.sh" and hitting the assertion failure.
    There's also a diff of the code compared to what I used to generate the
    "with-swms" results.


    Folder "no-swms-sc1-sc2"
    ------------------------

    Similar as above, but with the display link configured to use SC1 and SC2.
    Assertion failure is in the log.


    Folder "with-swms"
    ------------------

    Contains the logs of the code base _with_ the mosaicer still and hitting "i" on
    the ./run.sh console. Interval between information prints is ~15 seconds.
    There's also a diff between the version I started with and after I integrated
    all the changes I received from this thread.

    pschrader-send-logs-to-ti.zip
  • The changes look fine .Only thing is application is still feeding frames at only 30 fps doubling the latency due to OSA_waitMsecs(33); in demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis_bits_rd.c. This should be a low value like 1 ms (also try 16 ms/8 ms)).Additionally try setting  ipcBitsOutHLOSPrm.numBufPerCh = 2 (also try 3 )  so that there is minimal buffering in the pipeline.

     

  • Thanks for taking a look, Badri.

    Any thoughts on the assertion failures? It would be nice to be able to remove the mosaicer from the chain entirely.
    On that note, setting the mosaicer to output 420 as shown in the ./mcfw/src_linux/mcfw_api/usecases/ti810x/multich_progressive_4d1_vcap_venc_vdec_vdis.c causes an assertion failure during init as follows:
    ....
     [m3vpss ]  21719: SWMS: Create in progress !!!
     [m3vpss ]  UTILS: DMA: Allocated CH (TCC) = 58 (58)
     [m3vpss ]  UTILS: DMA: 0 of 1: Allocated PaRAM = 58 (0x49004740)
     [m3vpss ] SWMS: instance 0, sc id 4, start win 0 end win 3
     [m3vpss ]  21842: SWMS0    : Loading Vertical Co-effs (UPSCALE)x ...
     [m3vpss ]  21843: SWMS0    : Loading Horizontal Co-effs (UPSCALE)x ...
     [m3vpss ]  21843: SWMS    : Co-effs Loading ... DONE !!!
     [m3vpss ] SWMS: instance 1, sc id 7, start win 4 end win 21
     [m3vpss ]  21843: SWMS    : VipScReq is FALSE!!!
     [m3vpss ]  21844: Assertion @ Line: 2197 in links_m3vpss/swMs/swMsLink_drv.c: pDrvObj->fvidHandle != NULL : failed !!!

    I'm guessing it's simply missing some other initialization step, but I haven't dug into the error yet. Any thoughts?
    As a reference, this is what I added:

    +        swMsPrm[i].outDataFormat              = SYSTEM_DF_YUV420SP_UV;

    ----

    Regarding the OSA_waitMsecs(33); We added manual feeding of frames at 30fps on purpose to more accurately measure how long it takes a frame to go through the entire chain without anything preventing it from going through as fast as it can.

    I will try playing with the number of buffers. Though I can't find the exact variable you specified (i.e. ipcBitsOutHLOSPrm). The only candidates I can find in my code base are:

    a) ipcBitsOutHostPrm
    b) ipcBitsOutDspPrm
    c) ipcBitsOutVideoPrm

    Are any of those what you are recommending to modify?

    Thanks,
    Philipp

  • It is ipcBitsOutHostPrm

  • Hello,

    Are you using DM810x or DM816x?

    In RDK 3.5,  420 path display is supported for both 816x and  810x, but not supported for 814x.  

    Some changes are required in RDK display controller to support two independent 420 path displays.  I guess you use 816x with RDK 3.5, then use the attached patche

    Also, please share your file vps_init_ti816x.c (from hdvpss package), i want to review the same

    regards, Shiju

    7288.system_dctrl.c
    /*******************************************************************************
     *                                                                             *
     * Copyright (c) 2009 Texas Instruments Incorporated - http://www.ti.com/      *
     *                        ALL RIGHTS RESERVED                                  *
     *                                                                             *
     ******************************************************************************/
    
    
    /* ========================================================================== */
    /*                             Include Files                                  */
    /* ========================================================================== */
    
    #include "system_priv_m3vpss.h"
    #include <mcfw/interfaces/common_def/ti_vsys_common_def.h>
    #include <mcfw/interfaces/common_def/ti_vdis_common_def.h>
    #include "system_dctrl_modeInfo.h"
    
    #if defined(TI_816X_BUILD)
    /* Display Controller Configuration */
    /* To tie DVO2 and HDCOMP together refer following Mesh */
    Vps_DcConfig gSystem_dctrlTriDisplayConfigDvo2 = {
        VPS_DC_USERSETTINGS,                                   /* Use Case */
        /* Edge information */
        {
         {VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX}     ,
         {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP}     ,
         {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND}     ,
         {VPS_DC_BP1_INPUT_PATH, VPS_DC_HDCOMP_MUX}     ,
         {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT}     ,
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND}     ,
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDCOMP_BLEND}     ,
         {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX}     ,
         {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND}     ,
         {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND}     ,
         {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_HDCOMP_BLEND}     ,
         {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_DVO2_BLEND}
         }
        ,
        12,
        /* VENC information */
        {
         /* Mode information */
         {
          {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_DVO2, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
           }
          }
         ,
         (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP),              /* Tied VENC bit
                                                                * mask */
         4u                                                    /* Number of VENCs
                                                                */
         }
    };
    
    /* To tie HDMI and HDCOMP together refer following Mesh */
    Vps_DcConfig gSystem_dctrlTriDisplayConfigHdmi = {
        VPS_DC_USERSETTINGS,                                   /* Use Case */
        /* Edge information */
        {
         {VPS_DC_BP0_INPUT_PATH, VPS_DC_HDCOMP_MUX},
         {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT},
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDMI_BLEND},
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDCOMP_BLEND},
         {VPS_DC_BP1_INPUT_PATH, VPS_DC_VCOMP_MUX},
         {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
         {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_DVO2_BLEND},
         {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX},
         {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND},
         {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND},
         {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDCOMP_BLEND},
         {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_DVO2_BLEND},
         {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND},
         {VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
         {VPS_DC_AUX_INPUT_PATH, VPS_DC_HDCOMP_MUX}
         } ,
        15,
        /* VENC information */
        {
         /* Mode information */
         {
          {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_DVO2, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
           }
          }
         ,
         (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP),              /* Tied VENC bit
                                                                * mask */
         4u                                                    /* Number of VENCs */
         }
    };
    #endif
    
    
    #if defined(TI_814X_BUILD)
    /* Display Controller Configuration */
    /* To tie DVO2 and HDCOMP together refer following Mesh */
    Vps_DcConfig gSystem_dctrlTriDisplayConfig = {
        VPS_DC_USERSETTINGS,                                   /* Use Case */
        /* Edge information */
        {
         {VPS_DC_BP0_INPUT_PATH, VPS_DC_HDCOMP_MUX}     ,
         {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT}      ,
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDMI_BLEND}     ,
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND}     ,
         {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX}    ,
         {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND}       ,
         {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND}   ,
         {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_DVO2_BLEND}  ,
         {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND}
        }
    
        ,
        9,
        /* VENC information */
        {
         /* Mode information */
         {
          {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_DVO2, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
           }
          }
         ,
         (VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2),                /* Tied VENC bit
                                                                * mask */
         3u                                                    /* Number of VENCs
                                                                */
         }
    };
    #endif
    
    
    #if defined(TI_8107_BUILD)
    /* Display Controller Configuration */
    /* To tie DVO2 and HDCOMP together refer following Mesh */
    Vps_DcConfig gSystem_dctrlTriDisplayConfig = {
        VPS_DC_USERSETTINGS,                                   /* Use Case */
        /* Edge information */
        {
            {VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX},
            {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
            {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND},
            {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDCOMP_BLEND},
            {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX},
            {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND},
            {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND},
            {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDCOMP_BLEND},
            {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND},
    
            {VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
            {VPS_DC_AUX_INPUT_PATH, VPS_DC_VCOMP_MUX},
            {VPS_DC_BP1_INPUT_PATH, VPS_DC_SDVENC_MUX},
        },
    
        12,
        /* VENC information */
        {
         /* Mode information */
         {
          {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
          },                                                   /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
    
          {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
           }
          }
         ,
         (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP),                /* Tied VENC bit
                                                                * mask */
         3u                                                    /* Number of VENCs
                                                                */
         }
    };
    #endif
    
    
    
    Int32 System_getClk(UInt32 displayRes)
    {
        Int32 clkValue = VSYS_STD_MAX;
        switch(displayRes) {
            case VSYS_STD_1080P_30:
            case VSYS_STD_1080I_60:
                clkValue = 74250u;
            break;
            case VSYS_STD_720P_60:
                clkValue = 74250;
            break;
            case VSYS_STD_1080P_60:
            case VSYS_STD_1080P_50:
                clkValue = 148500u;
            break;
            case VSYS_STD_XGA_60:
                clkValue = 65000u;
            break;
            case VSYS_STD_SXGA_60:
                clkValue = 108000u;
            break;
            case VSYS_STD_SVGA_60:
                clkValue = 40000u;
            break;
            case VSYS_STD_PAL:
                clkValue = 27000u;
            break;
    
            default:
                UTILS_assert(0);
            break;
        }
        return(clkValue);
    }
    
    Int32 System_displayCtrlInit(VDIS_PARAMS_S * pPrm)
    {
    
        Int32                   driverRetVal, retVal;
        Vps_DcCreateConfig      dcCreateCfg;
        Vps_CscConfig           dcVcompCscConfig;
        Vps_CscConfig           dcHdcompCscConfig;
        Vps_CscConfig           dcSdCscConfig;
        Vps_DcEdeConfig         dcEdeCfg;
        Vps_DcVencClkSrc        clkSrc;
        Vps_DcConfig            *dctrlTriDisplayConfig = NULL;
    
    #if defined(TI_814X_BUILD)
        /* Need to set this bit only for ti814x to support tied vencs, pin mux settings */
        (* (UInt32 *)0x481C52C8) = 0x01000000;
    #endif
    
        System_displayUnderflowCheck(TRUE);
    #if defined(TI_814X_BUILD) || defined (TI_8107_BUILD)
        dctrlTriDisplayConfig = &(gSystem_dctrlTriDisplayConfig);
        dctrlTriDisplayConfig->vencInfo.tiedVencs = pPrm->tiedDevicesMask;
    #endif
    
    #ifdef TI_816X_BUILD
        if(pPrm->tiedDevicesMask == (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP))
        {
            dctrlTriDisplayConfig = &(gSystem_dctrlTriDisplayConfigHdmi);
            dctrlTriDisplayConfig->vencInfo.tiedVencs = pPrm->tiedDevicesMask;
        }
        if(pPrm->tiedDevicesMask == (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP))
        {
            dctrlTriDisplayConfig = &(gSystem_dctrlTriDisplayConfigDvo2);
            dctrlTriDisplayConfig->vencInfo.tiedVencs = pPrm->tiedDevicesMask;
        }
    #endif
        memcpy(&gSystem_objVpss.displayCtrlCfg, dctrlTriDisplayConfig, sizeof(Vps_DcConfig));
    
        gSystem_objVpss.enableConfigExtVideoEncoder = pPrm->enableConfigExtVideoEncoder;
    
    
        retVal = System_configVencInfo(pPrm);
        UTILS_assert(retVal == 0);
    
    //     /* Clock VENC_D is always tied to HDMI (DVO1)*/
        gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_D].outputClk =
                                    System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].resolution);
    
    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP)) {
            UTILS_assert (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].resolution);
                gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                         System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
         }
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP)) {
            UTILS_assert (pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].resolution == pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].resolution);
            gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                     System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
        }
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2)) {
            UTILS_assert (pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].resolution == pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
            gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                     System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].resolution);
        }
        if(!(dctrlTriDisplayConfig->vencInfo.tiedVencs)) {
                gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                         System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
         }
    #endif
    
        /* Configure pixel clock */
        retVal = System_dispSetPixClk();
        UTILS_assert(FVID2_SOK == retVal);
    
        dcVcompCscConfig.bypass  =
        dcHdcompCscConfig.bypass =
        dcSdCscConfig.bypass     = FALSE;
        dcVcompCscConfig.coeff   =
        dcHdcompCscConfig.coeff  =
        dcSdCscConfig.coeff      = NULL;
    
        dcVcompCscConfig.mode  =
        dcHdcompCscConfig.mode =
        dcSdCscConfig.mode     = pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].colorSpaceMode; //VPS_CSC_MODE_HDTV_GRAPHICS_Y2R;
    
        memset(&dcCreateCfg, 0, sizeof(dcCreateCfg));
    
        if (pPrm->enableEdgeEnhancement) {
            dcEdeCfg.ltiEnable = TRUE;
            dcEdeCfg.horzPeaking = TRUE;
            dcEdeCfg.ctiEnable = TRUE;
            dcEdeCfg.transAdjustEnable = TRUE;
            dcEdeCfg.lumaPeaking = TRUE;
            dcEdeCfg.chromaPeaking = TRUE;
            dcEdeCfg.minClipLuma = 0;
            dcEdeCfg.maxClipLuma = 1023;
            dcEdeCfg.minClipChroma = 0;
            dcEdeCfg.maxClipChroma = 1023;
            dcEdeCfg.bypass = FALSE;
    
            dcCreateCfg.edeConfig       = &dcEdeCfg;
        }
    
        dcCreateCfg.vcompCscConfig  = &dcVcompCscConfig;
        dcCreateCfg.hdcompCscConfig = &dcHdcompCscConfig;
        dcCreateCfg.sdCscConfig     = &dcSdCscConfig;
    
        /* Open and configure display controller */
        gSystem_objVpss.fvidDisplayCtrl = FVID2_create(
                          FVID2_VPS_DCTRL_DRV,
                          VPS_DCTRL_INST_0,
                          &dcCreateCfg,
                          &driverRetVal,
                          NULL);
        //GT_assert( GT_DEFAULT_MASK, NULL != gSystem_objVpss.fvidDisplayCtrl );
        UTILS_assert(NULL != gSystem_objVpss.fvidDisplayCtrl);
    
        /* Set output in display controller */
        if (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].enable) {
            retVal = FVID2_control(
                    gSystem_objVpss.fvidDisplayCtrl,
                    IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                    &pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].outputInfo,
                    NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    
        if (pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].enable) {
            retVal = FVID2_control(
                        gSystem_objVpss.fvidDisplayCtrl,
                        IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                        &pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].outputInfo,
                        NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    
        if (pPrm->deviceParams[SYSTEM_DC_VENC_SD].enable) {
            retVal = FVID2_control(
                        gSystem_objVpss.fvidDisplayCtrl,
                        IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                        &pPrm->deviceParams[SYSTEM_DC_VENC_SD].outputInfo,
                        NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    
    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
        if (pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].enable) {
    
    #ifdef TI816X_DVR
        /*set the HDCOMP to VGA output if it is DVR and PG2.0*/
           if (Vps_platformGetCpuRev() >= SYSTEM_PLATFORM_CPU_REV_2_0)
                pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].outputInfo.dvoFmt =
                       VPS_DC_DVOFMT_TRIPLECHAN_DISCSYNC;
    #endif
            retVal = FVID2_control(
                        gSystem_objVpss.fvidDisplayCtrl,
                        IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                        &pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].outputInfo,
                        NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    #endif
    
        /* Set the Clock source for VENC_DVO2 */
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2)) {
            /* Set the Clock source for DVO2 */
    
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
            /* Set the Clock source for HDCOMP */
            clkSrc.venc = VPS_DC_VENC_HDCOMP;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
    #endif
        }
    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
    
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP)) {
            /* Set the Clock source for off-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for VGA */
            clkSrc.venc = VPS_DC_VENC_HDCOMP;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
        }
    
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP)) {
            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for VGA */
            clkSrc.venc = VPS_DC_VENC_HDCOMP;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            // clkSrc is the same as HDMI for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for off-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
        }
    
    #endif
    
        if(!(dctrlTriDisplayConfig->vencInfo.tiedVencs)) {
            /* Set the Clock source for off-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
        }
    
        if(pPrm->enableConfigExtThsFilter == TRUE) {
    #ifdef SYSTEM_USE_VIDEO_DECODER
            System_Ths7360SfCtrl    thsCtrl;
    
            /* THS is tied to HDCOMP/HDDAC only for EVM */
            switch (gSystem_objVpss.displayCtrlCfg.vencInfo.modeInfo[1].mInfo.standard)
            {
                case FVID2_STD_720P_60:
                case FVID2_STD_720P_50:
                case FVID2_STD_1080I_60:
                case FVID2_STD_1080I_50:
                case FVID2_STD_1080P_30:
                    thsCtrl = SYSTEM_THS7360_SF_HD_MODE;
                    break;
    
                default:
                case FVID2_STD_1080P_60:
                case FVID2_STD_1080P_50:
                    thsCtrl = SYSTEM_THS7360_SF_TRUE_HD_MODE;
                    break;
            }
            System_ths7360SetSfParams(thsCtrl);
            System_ths7360SetSdParams(SYSTEM_THSFILTER_ENABLE_MODULE);
    #endif
        }
    
    #if defined(TI_8107_BUILD)
        retVal = System_platformSelectHdCompClkSrc(SYSTEM_VPLL_OUTPUT_VENC_A);
        UTILS_assert(retVal == FVID2_SOK);
    #endif
    
    #ifdef TI816X_DVR
        retVal = System_platformSelectHdCompSyncSrc(SYSTEM_HDCOMP_SYNC_SRC_DVO1, 1);
        UTILS_assert(retVal == FVID2_SOK);
    #endif
        retVal = FVID2_control(
                     gSystem_objVpss.fvidDisplayCtrl,
                     IOCTL_VPS_DCTRL_SET_CONFIG,
                     &gSystem_objVpss.displayCtrlCfg,
                     NULL);
        //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
        UTILS_assert(retVal == FVID2_SOK);
    
        if (gSystem_objVpss.enableConfigExtVideoEncoder)
        {
    #ifdef SYSTEM_USE_VIDEO_DECODER
    #ifndef TI8107_DVR
           if((pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == VSYS_STD_1080P_60) ||
               (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == VSYS_STD_720P_60)) {
                System_hdmiStart(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution, System_getBoardId());
            }
    #endif
    #endif
        }
    
    
        return retVal;
    }
    
    Int32 System_displayCtrlSetVencOutput(VDIS_DEV_PARAM_S * pPrm)
    {
        Int32 retVal = FVID2_SOK;
    
        /* Set output in display controller */
        if (pPrm->enable) {
            retVal = FVID2_control(
                    gSystem_objVpss.fvidDisplayCtrl,
                    IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                    &pPrm->outputInfo,
                    NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    
        return retVal;
    }
    
    Int32 System_displayCtrlDeInit(VDIS_PARAMS_S * pPrm)
    {
        Int32 retVal;
    
    #ifdef SYSTEM_USE_VIDEO_DECODER
    #ifndef TI8107_DVR
        if (gSystem_objVpss.enableConfigExtVideoEncoder)
        {
          if((pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == VSYS_STD_1080P_60) ||
               (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == VSYS_STD_720P_60)) {
                    System_hdmiStop();
             }
        }
    #endif
    #endif
    
    
        /* Remove and close display controller configuration */
        retVal = FVID2_control(gSystem_objVpss.fvidDisplayCtrl,
                               IOCTL_VPS_DCTRL_CLEAR_CONFIG,
                               &gSystem_objVpss.displayCtrlCfg, NULL);
        UTILS_assert(retVal == FVID2_SOK);
    
        retVal = FVID2_delete(gSystem_objVpss.fvidDisplayCtrl, NULL);
        UTILS_assert(retVal == FVID2_SOK);
    
        System_displayUnderflowPrint(FALSE, TRUE);
    
        return retVal;
    }
    
    
    

  • Hello

    sorry i have missed one change, used the updated system_dctrl.c attched here

    I have checked your logs

    no-swms-bp0-bp1 - this will not works as in this mode (BP0 and BP1) display accept only 422 input format 

    no-swms-sc1-sc2 - try with modified system_dctrl.c

    regards, shiju

  • Hi Shiju,

    It sounded like you wanted to attach another file to your last post. If that's the case, it appears to be missing.
    I will try out the system_dctrl.c file you've posted though.

    To answer your other question: I'm using RDK 3.5 with a DM8168.

    Please find attached my vps_init_ti816x.c from the hdvpss package.

    Thanks,
    Philipp

  • Hi Shiju,

    I tried the 7288.system_dctrl.c that you linked. It appears that the same assertion failures still happen.

    It sounded like you intended to upload another version of this file. Is that correct?

    Thanks,
    Philipp

  • Hi Philip,

     

    Could you share the log containing assertion?

     

    Regards,

    Brijesh

  • Hi Philip,

    sorry here attached the correct file, 

    Your vps_init_ti816x.c is correct and have necessary changes to support 420 path displays

    6712.system_dctrl.c
    /*******************************************************************************
     *                                                                             *
     * Copyright (c) 2009 Texas Instruments Incorporated - http://www.ti.com/      *
     *                        ALL RIGHTS RESERVED                                  *
     *                                                                             *
     ******************************************************************************/
    
    
    /* ========================================================================== */
    /*                             Include Files                                  */
    /* ========================================================================== */
    
    #include "system_priv_m3vpss.h"
    #include <mcfw/interfaces/common_def/ti_vsys_common_def.h>
    #include <mcfw/interfaces/common_def/ti_vdis_common_def.h>
    #include "system_dctrl_modeInfo.h"
    
    #if defined(TI_816X_BUILD)
    /* Display Controller Configuration */
    /* To tie DVO2 and HDCOMP together refer following Mesh */
    Vps_DcConfig gSystem_dctrlTriDisplayConfigDvo2 = {
        VPS_DC_USERSETTINGS,                                   /* Use Case */
        /* Edge information */
        {
         {VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX}     ,
         {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP}     ,
         {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND}     ,
         {VPS_DC_BP1_INPUT_PATH, VPS_DC_HDCOMP_MUX}     ,
         {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT}     ,
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND}     ,
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDCOMP_BLEND}     ,
         {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX}     ,
         {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND}     ,
         {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND}     ,
         {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_HDCOMP_BLEND}     ,
         {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_DVO2_BLEND},
         {VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
         {VPS_DC_AUX_INPUT_PATH, VPS_DC_HDCOMP_MUX}
         }
        ,
        14,
        /* VENC information */
        {
         /* Mode information */
         {
          {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_DVO2, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
           }
          }
         ,
         (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP),              /* Tied VENC bit
                                                                * mask */
         4u                                                    /* Number of VENCs
                                                                */
         }
    };
    
    /* To tie HDMI and HDCOMP together refer following Mesh */
    Vps_DcConfig gSystem_dctrlTriDisplayConfigHdmi = {
        VPS_DC_USERSETTINGS,                                   /* Use Case */
        /* Edge information */
        {
         {VPS_DC_BP0_INPUT_PATH, VPS_DC_HDCOMP_MUX},
         {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT},
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDMI_BLEND},
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDCOMP_BLEND},
         {VPS_DC_BP1_INPUT_PATH, VPS_DC_VCOMP_MUX},
         {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
         {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_DVO2_BLEND},
         {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX},
         {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND},
         {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND},
         {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDCOMP_BLEND},
         {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_DVO2_BLEND},
         {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND},
         {VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
         {VPS_DC_AUX_INPUT_PATH, VPS_DC_HDCOMP_MUX}
         } ,
        15,
        /* VENC information */
        {
         /* Mode information */
         {
          {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_DVO2, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
           }
          }
         ,
         (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP),              /* Tied VENC bit
                                                                * mask */
         4u                                                    /* Number of VENCs */
         }
    };
    #endif
    
    
    #if defined(TI_814X_BUILD)
    /* Display Controller Configuration */
    /* To tie DVO2 and HDCOMP together refer following Mesh */
    Vps_DcConfig gSystem_dctrlTriDisplayConfig = {
        VPS_DC_USERSETTINGS,                                   /* Use Case */
        /* Edge information */
        {
         {VPS_DC_BP0_INPUT_PATH, VPS_DC_HDCOMP_MUX}     ,
         {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT}      ,
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDMI_BLEND}     ,
         {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND}     ,
         {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX}    ,
         {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND}       ,
         {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND}   ,
         {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_DVO2_BLEND}  ,
         {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND}
        }
    
        ,
        9,
        /* VENC information */
        {
         /* Mode information */
         {
          {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_DVO2, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
           }
          }
         ,
         (VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2),                /* Tied VENC bit
                                                                * mask */
         3u                                                    /* Number of VENCs
                                                                */
         }
    };
    #endif
    
    
    #if defined(TI_8107_BUILD)
    /* Display Controller Configuration */
    /* To tie DVO2 and HDCOMP together refer following Mesh */
    Vps_DcConfig gSystem_dctrlTriDisplayConfig = {
        VPS_DC_USERSETTINGS,                                   /* Use Case */
        /* Edge information */
        {
            {VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX},
            {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
            {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND},
            {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDCOMP_BLEND},
            {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX},
            {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND},
            {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND},
            {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDCOMP_BLEND},
            {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND},
    
            {VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
            {VPS_DC_AUX_INPUT_PATH, VPS_DC_VCOMP_MUX},
            {VPS_DC_BP1_INPUT_PATH, VPS_DC_SDVENC_MUX},
        },
    
        12,
        /* VENC information */
        {
         /* Mode information */
         {
          {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
          },                                                   /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
    
          {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
           }
          }
         ,
         (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP),                /* Tied VENC bit
                                                                * mask */
         3u                                                    /* Number of VENCs
                                                                */
         }
    };
    #endif
    
    
    
    Int32 System_getClk(UInt32 displayRes)
    {
        Int32 clkValue = VSYS_STD_MAX;
        switch(displayRes) {
            case VSYS_STD_1080P_30:
            case VSYS_STD_1080I_60:
                clkValue = 74250u;
            break;
            case VSYS_STD_720P_60:
                clkValue = 74250;
            break;
            case VSYS_STD_1080P_60:
            case VSYS_STD_1080P_50:
                clkValue = 148500u;
            break;
            case VSYS_STD_XGA_60:
                clkValue = 65000u;
            break;
            case VSYS_STD_SXGA_60:
                clkValue = 108000u;
            break;
            case VSYS_STD_SVGA_60:
                clkValue = 40000u;
            break;
            case VSYS_STD_PAL:
                clkValue = 27000u;
            break;
    
            default:
                UTILS_assert(0);
            break;
        }
        return(clkValue);
    }
    
    Int32 System_displayCtrlInit(VDIS_PARAMS_S * pPrm)
    {
    
        Int32                   driverRetVal, retVal;
        Vps_DcCreateConfig      dcCreateCfg;
        Vps_CscConfig           dcVcompCscConfig;
        Vps_CscConfig           dcHdcompCscConfig;
        Vps_CscConfig           dcSdCscConfig;
        Vps_DcEdeConfig         dcEdeCfg;
        Vps_DcVencClkSrc        clkSrc;
        Vps_DcConfig            *dctrlTriDisplayConfig = NULL;
    
    #if defined(TI_814X_BUILD)
        /* Need to set this bit only for ti814x to support tied vencs, pin mux settings */
        (* (UInt32 *)0x481C52C8) = 0x01000000;
    #endif
    
        System_displayUnderflowCheck(TRUE);
    #if defined(TI_814X_BUILD) || defined (TI_8107_BUILD)
        dctrlTriDisplayConfig = &(gSystem_dctrlTriDisplayConfig);
        dctrlTriDisplayConfig->vencInfo.tiedVencs = pPrm->tiedDevicesMask;
    #endif
    
    #ifdef TI_816X_BUILD
        if(pPrm->tiedDevicesMask == (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP))
        {
            dctrlTriDisplayConfig = &(gSystem_dctrlTriDisplayConfigHdmi);
            dctrlTriDisplayConfig->vencInfo.tiedVencs = pPrm->tiedDevicesMask;
        }
        if(pPrm->tiedDevicesMask == (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP))
        {
            dctrlTriDisplayConfig = &(gSystem_dctrlTriDisplayConfigDvo2);
            dctrlTriDisplayConfig->vencInfo.tiedVencs = pPrm->tiedDevicesMask;
        }
    #endif
        memcpy(&gSystem_objVpss.displayCtrlCfg, dctrlTriDisplayConfig, sizeof(Vps_DcConfig));
    
        gSystem_objVpss.enableConfigExtVideoEncoder = pPrm->enableConfigExtVideoEncoder;
    
    
        retVal = System_configVencInfo(pPrm);
        UTILS_assert(retVal == 0);
    
    //     /* Clock VENC_D is always tied to HDMI (DVO1)*/
        gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_D].outputClk =
                                    System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].resolution);
    
    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP)) {
            UTILS_assert (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].resolution);
                gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                         System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
         }
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP)) {
            UTILS_assert (pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].resolution == pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].resolution);
            gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                     System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
        }
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2)) {
            UTILS_assert (pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].resolution == pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
            gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                     System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].resolution);
        }
        if(!(dctrlTriDisplayConfig->vencInfo.tiedVencs)) {
                gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                         System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
         }
    #endif
    
        /* Configure pixel clock */
        retVal = System_dispSetPixClk();
        UTILS_assert(FVID2_SOK == retVal);
    
        dcVcompCscConfig.bypass  =
        dcHdcompCscConfig.bypass =
        dcSdCscConfig.bypass     = FALSE;
        dcVcompCscConfig.coeff   =
        dcHdcompCscConfig.coeff  =
        dcSdCscConfig.coeff      = NULL;
    
        dcVcompCscConfig.mode  =
        dcHdcompCscConfig.mode =
        dcSdCscConfig.mode     = pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].colorSpaceMode; //VPS_CSC_MODE_HDTV_GRAPHICS_Y2R;
    
        memset(&dcCreateCfg, 0, sizeof(dcCreateCfg));
    
        if (pPrm->enableEdgeEnhancement) {
            dcEdeCfg.ltiEnable = TRUE;
            dcEdeCfg.horzPeaking = TRUE;
            dcEdeCfg.ctiEnable = TRUE;
            dcEdeCfg.transAdjustEnable = TRUE;
            dcEdeCfg.lumaPeaking = TRUE;
            dcEdeCfg.chromaPeaking = TRUE;
            dcEdeCfg.minClipLuma = 0;
            dcEdeCfg.maxClipLuma = 1023;
            dcEdeCfg.minClipChroma = 0;
            dcEdeCfg.maxClipChroma = 1023;
            dcEdeCfg.bypass = FALSE;
    
            dcCreateCfg.edeConfig       = &dcEdeCfg;
        }
    
        dcCreateCfg.vcompCscConfig  = &dcVcompCscConfig;
        dcCreateCfg.hdcompCscConfig = &dcHdcompCscConfig;
        dcCreateCfg.sdCscConfig     = &dcSdCscConfig;
    
        /* Open and configure display controller */
        gSystem_objVpss.fvidDisplayCtrl = FVID2_create(
                          FVID2_VPS_DCTRL_DRV,
                          VPS_DCTRL_INST_0,
                          &dcCreateCfg,
                          &driverRetVal,
                          NULL);
        //GT_assert( GT_DEFAULT_MASK, NULL != gSystem_objVpss.fvidDisplayCtrl );
        UTILS_assert(NULL != gSystem_objVpss.fvidDisplayCtrl);
    
        /* Set output in display controller */
        if (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].enable) {
            retVal = FVID2_control(
                    gSystem_objVpss.fvidDisplayCtrl,
                    IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                    &pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].outputInfo,
                    NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    
        if (pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].enable) {
            retVal = FVID2_control(
                        gSystem_objVpss.fvidDisplayCtrl,
                        IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                        &pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].outputInfo,
                        NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    
        if (pPrm->deviceParams[SYSTEM_DC_VENC_SD].enable) {
            retVal = FVID2_control(
                        gSystem_objVpss.fvidDisplayCtrl,
                        IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                        &pPrm->deviceParams[SYSTEM_DC_VENC_SD].outputInfo,
                        NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    
    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
        if (pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].enable) {
    
    #ifdef TI816X_DVR
        /*set the HDCOMP to VGA output if it is DVR and PG2.0*/
           if (Vps_platformGetCpuRev() >= SYSTEM_PLATFORM_CPU_REV_2_0)
                pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].outputInfo.dvoFmt =
                       VPS_DC_DVOFMT_TRIPLECHAN_DISCSYNC;
    #endif
            retVal = FVID2_control(
                        gSystem_objVpss.fvidDisplayCtrl,
                        IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                        &pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].outputInfo,
                        NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    #endif
    
        /* Set the Clock source for VENC_DVO2 */
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2)) {
            /* Set the Clock source for DVO2 */
    
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
            /* Set the Clock source for HDCOMP */
            clkSrc.venc = VPS_DC_VENC_HDCOMP;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
    #endif
        }
    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
    
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP)) {
            /* Set the Clock source for off-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for VGA */
            clkSrc.venc = VPS_DC_VENC_HDCOMP;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
        }
    
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP)) {
            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for VGA */
            clkSrc.venc = VPS_DC_VENC_HDCOMP;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            // clkSrc is the same as HDMI for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for off-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
        }
    
    #endif
    
        if(!(dctrlTriDisplayConfig->vencInfo.tiedVencs)) {
            /* Set the Clock source for off-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    
        }
    
        if(pPrm->enableConfigExtThsFilter == TRUE) {
    #ifdef SYSTEM_USE_VIDEO_DECODER
            System_Ths7360SfCtrl    thsCtrl;
    
            /* THS is tied to HDCOMP/HDDAC only for EVM */
            switch (gSystem_objVpss.displayCtrlCfg.vencInfo.modeInfo[1].mInfo.standard)
            {
                case FVID2_STD_720P_60:
                case FVID2_STD_720P_50:
                case FVID2_STD_1080I_60:
                case FVID2_STD_1080I_50:
                case FVID2_STD_1080P_30:
                    thsCtrl = SYSTEM_THS7360_SF_HD_MODE;
                    break;
    
                default:
                case FVID2_STD_1080P_60:
                case FVID2_STD_1080P_50:
                    thsCtrl = SYSTEM_THS7360_SF_TRUE_HD_MODE;
                    break;
            }
            System_ths7360SetSfParams(thsCtrl);
            System_ths7360SetSdParams(SYSTEM_THSFILTER_ENABLE_MODULE);
    #endif
        }
    
    #if defined(TI_8107_BUILD)
        retVal = System_platformSelectHdCompClkSrc(SYSTEM_VPLL_OUTPUT_VENC_A);
        UTILS_assert(retVal == FVID2_SOK);
    #endif
    
    #ifdef TI816X_DVR
        retVal = System_platformSelectHdCompSyncSrc(SYSTEM_HDCOMP_SYNC_SRC_DVO1, 1);
        UTILS_assert(retVal == FVID2_SOK);
    #endif
        retVal = FVID2_control(
                     gSystem_objVpss.fvidDisplayCtrl,
                     IOCTL_VPS_DCTRL_SET_CONFIG,
                     &gSystem_objVpss.displayCtrlCfg,
                     NULL);
        //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
        UTILS_assert(retVal == FVID2_SOK);
    
        if (gSystem_objVpss.enableConfigExtVideoEncoder)
        {
    #ifdef SYSTEM_USE_VIDEO_DECODER
    #ifndef TI8107_DVR
           if((pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == VSYS_STD_1080P_60) ||
               (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == VSYS_STD_720P_60)) {
                System_hdmiStart(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution, System_getBoardId());
            }
    #endif
    #endif
        }
    
    
        return retVal;
    }
    
    Int32 System_displayCtrlSetVencOutput(VDIS_DEV_PARAM_S * pPrm)
    {
        Int32 retVal = FVID2_SOK;
    
        /* Set output in display controller */
        if (pPrm->enable) {
            retVal = FVID2_control(
                    gSystem_objVpss.fvidDisplayCtrl,
                    IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                    &pPrm->outputInfo,
                    NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    
        return retVal;
    }
    
    Int32 System_displayCtrlDeInit(VDIS_PARAMS_S * pPrm)
    {
        Int32 retVal;
    
    #ifdef SYSTEM_USE_VIDEO_DECODER
    #ifndef TI8107_DVR
        if (gSystem_objVpss.enableConfigExtVideoEncoder)
        {
          if((pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == VSYS_STD_1080P_60) ||
               (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == VSYS_STD_720P_60)) {
                    System_hdmiStop();
             }
        }
    #endif
    #endif
    
    
        /* Remove and close display controller configuration */
        retVal = FVID2_control(gSystem_objVpss.fvidDisplayCtrl,
                               IOCTL_VPS_DCTRL_CLEAR_CONFIG,
                               &gSystem_objVpss.displayCtrlCfg, NULL);
        UTILS_assert(retVal == FVID2_SOK);
    
        retVal = FVID2_delete(gSystem_objVpss.fvidDisplayCtrl, NULL);
        UTILS_assert(retVal == FVID2_SOK);
    
        System_displayUnderflowPrint(FALSE, TRUE);
    
        return retVal;
    }
    
    
    

    try with this system_dctrl.c


    regards, shiju


  • My apologies for not getting back to anyone yesterday; it was a busy day.

    Brijesh, I should have clarified that the assertion failures were the same as the ones that I've uploaded earlier (no-smws-bp0-bp1 and no-swms-sc1-sc2).

    Shiju, thanks for the new file! I will try this.

  • Alright, this is working quite well! Thanks Shiju! I applied the new file and am seeing an improvement of roughly 10 ms.

    Unfortunately, there appears to be a corruption of pixels of about 20 pixels along the left and top border. I will try to get a picture of what I mean. Is there a utility with which I can do a capture of the display?

  • I've attached two pictures to illustrate what is going on.

    It looks like the whole picture is shifted by something like 20 pixels down and to the right.
    In other words, the bottom edge and right edge are cut off.
    In the left and top edges, there's duplicated pixels there.

    Do you have any thoughts on what's going on? I will investigate to see if I've misconfigured anything.

    Thanks,
    Philipp

    pschrader_corruption_pictures.zip
  • Can you apply below patch and check if it resolves the issue:

     

    ------------ mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c ------------
    diff --git a/mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c b/mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c
    index c7e29e6..74a9997 100755
    --- a/mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c
    +++ b/mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c
    @@ -251,6 +251,11 @@
         rtParams = freeFrameList->perListCfg;
         if (rtParams)
         {
    +        if (DisplayLink_drvIsDeiDisplayDrv(pObj))
    +        {
    +            rtParams = (UInt32)rtParams - (sizeof(Vps_DispRtParams) + sizeof(Vps_FrameParams));
    +        }
    +
             UTILS_COMPILETIME_ASSERT(
               offsetof(DisplayLink_drvRtParams,dispRtPrms) == 0);
             UTILS_assert(UTILS_ARRAYISVALIDENTRY(rtParams,pObj->rtParams.paramsMem));

  • Thanks Badri, I will try this and let you know what happens.

  • Looks like this was part of the changes you made for us on the displayLink module. (i.e. 0576.pschrader_dvr_rdk_display.zip)

    I can try removing it again, but I'm assuming it's quite necessary.

  • Would either of you happen to have any thoughts on this corruption?

    I can upload my code changes if that helps.