AM3359 RGMII with PHY RTL8211CL problem

I design a board with AM3359 process, and designed two ethernet port with RGMII interface to PHY RTL8211CL. and delay by RTL8211CL, the AM3359 initialize as follow:

1. Control Module RGMII_SELECT for 0x3A select the RGMII without internal delay

2.init rgmii1_pin_mux and rgmii2_pin_mux

3.MDIOInit

4.enable GPMACS clocks

5.init the ALE port and sliver etc

and the problem is:

The RGMII 's TCLK 25M clock is ok (Test by TDS2012 oscilloscope )

but when I send DHCP request the TXD0,1,2,3 always stay low, but the CPDMA_DESC_OWNER bit have cleared and tx_chan.hdp have cleared

The software refer from the AM335X_StarterWare_02_00_00_07