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IBIS DDR3 TMS320C6678 models

Torben Rasmussen
Prodigy 110 points
Other Parts Discussed in Thread: TMS320C6678

Where to locate the DDR3 IBIS models for the TMS320C6678

From SPRABI1B—May 2014

5.4 TI Commitment
Texas Instruments has taken the initiative toprovide IBIS models compliant with the
latest 5.0 IBIS standard for the DDR3 interface. The Texas Instruments DSP IBIS model
will be correlated to internal Matlab or Spice models, and functionally against timing
and performance parameters prior to release (TMS).


The questions is where to locate the models, (SPRM537)


But as fare as i can see there are no DDR3 models available in there.

  • 0
    TI__Guru* 81335 points

    Hi Torben,

    Moved this thread to correct forum.

    You shall find IBIS Models in TI product folder. Please refer Section "Models" under "Tools & Software".

    http://www.ti.com/product/TMS320C6678/toolssoftware

    Thank you.

  • 0 in reply to Raja
    Prodigy 110 points

    Hi

    Yes i know that this is normaly to be found there but the IBIS files there includes no models named DDR3, is "CSCDVGPBFZ_xxxx" to be used?

    Best regards

    Torben

  • 0 in reply to Torben Rasmussen
    TI__Mastermind 42545 points

    Hi Torben,

    The IBIS model for the C6678 contains models for each of the DDR3 address, command and data pins. I'm not sure what you are asking.

    Regards, Bill

  • 0 in reply to Bill Taboada
    TI__Expert 8715 points

    Torben,

    You are on the right path. The sub-models to choose depend on the DDR buffer operation mode (Drive strength, ODT and pulls, and the input setting of the two slew rate pins DDRSLRATE0 and DDRSLRATE1).
    However, I cannot explain if the IBIS doc has typos for SR0/SR1 values since they seem to have the same values for all slew rate settings.
    -Maybe Bill can comment on this?

    The IBIS model for example of DDRD00 [E28] uses

    [Model Selector] bshtltcscdvgpbfz  |  bshtltcscdvgpbfz.ibs [15 July 2011 Revision 1.4]
    CSCDVGPBFZ_FASTEST_10MA_5PER   TX 40 ohms Fast (SR0 1; SR1 0)
    CSCDVGPBFZ_FASTEST_9MA_5PER     TX 45 ohms Fast (SR0 1; SR1 0)
    CSCDVGPBFZ_FAST_10MA_5PER          TX 40 ohms Fast (SR0 1; SR1 0)
    CSCDVGPBFZ_SLOW_10MA_5PER        TX 40 ohms Fast (SR0 1; SR1 0)
    :

    that maps to register bits described in "KeyStone Architecture DDR3 Memory Controller User Guide SPRUGV8D—April 2014" - Table 4-5 SDRAM Configuration Register (SDCFG) Field Descriptions (Part 1 of 3)

    DDR_TERM
    DYN_ODT
    SDRAM_DRIVE = RQZ/6 (40ohm) or RQZ/7 (34ohm)

    RQZ is nominally 240Ohm, and you can read more about the buffer stages in "DDR3 Design Requirements for KeyStone Devices Application Report SPRABI1B May 2014 " - 4.5.1.1 Data Group Signals

    Slew rate control pins (Fastest/Fast/Slow/Slowest) are described in "Hardware Design Guide for KeyStone I Devices Application Report SPRABI2C August 2013 " - Table 30 Slew Rate Control

    I hope this gives more guidance.
    Cheers.

    /Magnus Aman

  • 0 in reply to M.A.M
    TI__Mastermind 42545 points

    Hi Torben,

    As Magnus pointed out in his excellent post, the SR settings in the model selector statement are not correct. The correct values can be found in the model selector statement for the bshtltcscddvgpbfz model. I'll put in a note to get that updated. The comment in the C6657 IBIS file is appropriate so I will copy that here.

    | The DDR3
    | Definitions:
    | Drive strength defined by resistor value connected to PTV15 pin
    | 9MA_FT9MA : Full Termination Thevenin [45 ohm] [45ohm to Vtt]
    |
    | Slew Rate Definitions:
    | The Driver Slew Rate is defined by the value of the DDRSLRATE0 and
    | DDRSLRATE1 pins.
    |
    | FASTEST Slew Rate : SR1 0;SR0 0
    | FAST Slew Rate : SR1 0;SR0 1
    | SLOW Slew Rate : SR1 1;SR0 0
    | SLOWEST Slew Rate : SR1 1;SR0 1
    |
    | To choose the correct model, determine the settings of the DDRSLRATE[1:0]
    | pins. Look for the keyword from the tables above to select the proper
    | models. For example if the DDRSLRATE1 pin is pulled high and the
    | DDRSLRATE0 pin is pulled low then the slew rate keyword is SLOW. For
    | this example the model needed for the address and control pins would be
    | CSCDVG_SLOW_9MA, the data and DQM pins would be CSCDVG_SLOW_9MA_FT9MA and
    | the DQS pins would be CSCDDVG_SLOW_9MA_FT9MA_N and CSCDDVG_SLOW_9MA_FT9MA_P.

    Regards, Bill