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AM3352: DDR3 IBIS model issues

Paul Koudritsk
Prodigy 20 points
Part Number: AM3352

Hi.

We are making some simulations for trace length adjustment and per the link below we are using the suggested models :

 

http://processors.wiki.ti.com/index.php/How_to_use_the_AM335x_IBIS_Models

 

DATA :

DQ

Model_352

3-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5

 

DQS _ nDQS :

DQS

Model_655

3-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_PADP_5PER_1P5

DQS#

Model_847

3-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_PADN_5PER_1P5

Due to that the trace length of the DQS nDQS pair is substantially different from the trace length of the DATA lines.

Want to confirm that it is the right direction since it was not the case for another vendor parts we had been working with before.

We have also analyzed the gerbers of the beaglebone black and it looks like there the DQS nDQS pair is matched in the length to the DATA lines.

Pls advise on this controversy.

  • 0
    TI__Guru**** 393215 points
    Hi,

    Please follow the guidelines given in section 7.7.2.3 of the AM335x Datasheet Rev. J. This is the leading document for DDR3 design with AM335x.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 20 points
    Thank you Biser.
    This is what I did and the result contradicts the simulation , from the past I trust simulation more.
    Pls confirm that the models suggested here ( link below ) are the correct models for simulation , it also clearly means that the DQS nDQS pair length will differ from the DATA lines length due to difference in the model drive strength.

    processors.wiki.ti.com/.../How_to_use_the_AM335x_IBIS_Models

    DATA :
    DQ Model_352 3-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5

    DQS _ nDQS :
    DQS Model_655 3-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_PADP_5PER_1P5
    DQS# Model_847 3-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_PADN_5PER_1P5


    Regards.
    Paul
  • 0 in reply to Paul Koudritsk
    TI__Mastermind 42545 points
    Hi Paul,
    The IBIS models provided by TI are sufficient for testing the signal integrity of DDR but are not qualified for doing timing analysis. The routing requirements must be met for robust operation. If you are basing you expectation for timing on you simulation, you may not be getting valid result.
    Regards, Bill