C5000 McBSP configuration did not work

Dear all,

I am trying to configure McBSP on C5509A to interface with a data stream from another peripheral with timing presented below, in which:

- Clkx and fsx, clkr and fsr are all fed from the peripheral

- The frame length is 1, the word length is 16, the  transmit and receive data delays are both =1

- Data is received on DSP at the falling edge of clkr, while data is transmitted on the rising edge of clkx.

For these configuration, in the image, the data is "0011101010111101"

I constructed the according McBSP configuration as follows

/* CSL config structure for MCBSP 1 */
static MCBSP_Config mcbspCfg0 = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF, /* DLB = 0 */
MCBSP_SPCR1_RJUST_RZF, /* RJUST = 0 */
MCBSP_SPCR1_CLKSTP_DISABLE, /* CLKSTP = 0 */
MCBSP_SPCR1_DXENA_NA, /* DXENA = 0 */
MCBSP_SPCR1_ABIS_DISABLE, /* ABIS = 0 */
MCBSP_SPCR1_RINTM_RRDY, /* RINTM = 0 */
0, /* RSYNCER = 0 */
MCBSP_SPCR1_RRST_DISABLE /* RRST = 0 */
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_YES, /* FREE = 1 */
MCBSP_SPCR2_SOFT_YES, /* SOFT = 1 */
MCBSP_SPCR2_FRST_FSG, /* FRST = 0 */
MCBSP_SPCR2_GRST_CLKG, /* GRST = 0 */
MCBSP_SPCR2_XINTM_XRDY, /* XINTM = 0 */
0, /* XSYNCER = 0 */
MCBSP_SPCR2_XRST_DISABLE /* XRST = 0 */
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(0), /* RFRLEN1 = 0 */
MCBSP_RCR1_RWDLEN1_16BIT /* RWDLEN1 = 5 */
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE, /* RPHASE = 0 */
MCBSP_RCR2_RFRLEN2_OF(0), /* RFRLEN2 = 0 */
MCBSP_RCR2_RWDLEN2_16BIT, /* RWDLEN2 = 0 */
//MCBSP_RCR2_RCOMPAND_ALAW,
MCBSP_RCR2_RCOMPAND_MSB, /* RCOMPAND = 0 */
MCBSP_RCR2_RFIG_YES, /* RFIG = 0 */
MCBSP_RCR2_RDATDLY_1BIT /* RDATDLY = 1 */
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(0), /* XFRLEN1 = 0 */
MCBSP_XCR1_XWDLEN1_16BIT /* XWDLEN1 = 2 */

),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE, /* XPHASE = 0 */
MCBSP_XCR2_XFRLEN2_OF(0), /* XFRLEN2 = 0 */
MCBSP_XCR2_XWDLEN2_16BIT, /* XWDLEN2 = 0 */
//MCBSP_XCR2_XCOMPAND_ALAW,
MCBSP_XCR2_XCOMPAND_MSB, /* XCOMPAND = 0 */
MCBSP_XCR2_XFIG_YES, /* XFIG = 0 */
MCBSP_XCR2_XDATDLY_1BIT /* XDATDLY = 1 */
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(0), /* FWID = 0 */
MCBSP_SRGR1_CLKGDV_OF(0) /* CLKGDV = 0 */
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE, /* FREE = 0 */
MCBSP_SRGR2_CLKSP_RISING, /* CLKSP = 0 */
MCBSP_SRGR2_CLKSM_CLKS, /* CLKSM = 0 */
MCBSP_SRGR2_FSGM_DXR2XSR, /* FSGM = 0 */ /*paired with MCBSP_PCR_FSXM_INTERNALL (FSXM=1) - FSXM and FSGM select the source of transmit frame-sync pulses, see page 52*/
MCBSP_SRGR2_FPER_OF( 0 ) /* FPER = 0 */ /*since all are generated from clkr and fsr - this parametter is of no meaning*/
),
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_IDLEEN_RESET, /* IDLEEN = 0 */
MCBSP_PCR_XIOEN_SP, /* XIOEN = 0 */
MCBSP_PCR_RIOEN_SP, /* RIOEN = 0 */
MCBSP_PCR_FSXM_EXTERNAL, /* FSXM = 0 */
MCBSP_PCR_FSRM_EXTERNAL, /* FSRM = 0 */
MCBSP_PCR_CLKXM_INPUT, /* CLKXM = 0 */
MCBSP_PCR_CLKRM_INPUT, /* CLKRM = 0 */
MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 */
0, /* DXSTAT = N/A */
MCBSP_PCR_FSXP_ACTIVEHIGH, /* See Figure 2-7. Single-Phase Frame for a McBSP Data Transfer, pagae 35*/
MCBSP_PCR_FSRP_ACTIVEHIGH,
MCBSP_PCR_CLKXP_RISING,
MCBSP_PCR_CLKRP_FALLING
),

MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};

but the program did not work. Could any of you please correct my mistake? I would appreciate it much?

With best regards,

Nguyen Anh Duc