Hi,
I wanted to understand how the DMA samples the I2S word clock. This is my scenario,
result = DMA_start(&gDMA_Rx_I2S0_L);
result = DMA_start(&gDMA_Rx_I2S0_R);
result = DMA_start(&gDMA_Rx_I2S1_L);
result = DMA_start(&gDMA_Rx_I2S1_R);
followed by:
I2S_transEnable(gI2S0, TRUE);
I2S_transEnable(gI2S1, TRUE);
- How does the WCLK start ? Could it potentially trigger a sample capture before I2S1 WCLK starts ?
- How can I synchronize them to make sure that the sample captures dont start until the next WCLK edge ?
Ron