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C5535 synchronous DMA capture across I2S0, I2S1

Hi,

I wanted to understand how the DMA samples the I2S word clock. This is my scenario,

        result = DMA_start(&gDMA_Rx_I2S0_L);
        result = DMA_start(&gDMA_Rx_I2S0_R);
        result = DMA_start(&gDMA_Rx_I2S1_L);
        result = DMA_start(&gDMA_Rx_I2S1_R);
followed by:

        I2S_transEnable(gI2S0, TRUE);
        I2S_transEnable(gI2S1, TRUE);

- How does the WCLK start ? Could it potentially trigger a sample capture before I2S1 WCLK starts ?

- How can I synchronize them to make sure that the sample captures dont start until the next WCLK edge ?

Ron

  • Hi Ron,

    We will address your request shortly.

    Thanks & regards,

    Sivaraj K

  • Hi,

    Below is how the I2S DMA operation is performed.

    When the required number of data words is received in the Receive Shift register (one for mono or two for stereo), the data is moved into the Receive Buffer register and ultimately into the Receive Left/Right Data1/0 registers. A receive interrupt/event is generated at this point. The DMA servicing this interrupt/event reads the register into memory. Failure to do so before the next frame-sync cycle will result in the OUERROR being flagged in the I2SINTFL register (assuming that error detection has been enabled in the I2SINTMASK register).

    On your other questions on WCLK Start and Synchronization.

    WCLK will start once proper I2S configuration is done and Enable bit is set in the I2SSCTRL Register. As mentioned above the event would get generated/triggered based on the respective transmit/receive data being transmited/received.

    You could refer to I2S DMA CSL example which illustrates the configuartion and also helps you understand on how I2S transmit and Receive are performed using DMA.

    The CSL example can be downloaded and installed from the below link.

    http://www.ti.com/tool/sprc133

    Hope the above information helps.

    Regards

     Vasanth