Hello, we are using sitara GPMC in synchronous mode to communicate with FPGA. Could someone please clarify the timing characteristics for a synchronous write, outlined in Table 7-22 in AM335x Datasheet.
The 'F15' timing parameter: "Delay time, output clock gpmc_clk rising edge to output data gpmc_ad[15:0] transition. is specified as ' J-2.3 <= F15 <= J + 1.9'.
Since J = 10 ns (constant), does this mean that the gpmc_ad transition will fall on the negative edge of GPMC_CLK if the clock period is set to 20ns?