DEVSPEED on the EVMK2H board default to 0?

RobbySun

Hi,

I'd like to confirm what I am getting is correct. I am using an EVMK2H board. The board features a single 66AK2H14 SoC chip, with 4X Cortex-A15 + 8X C66x cores. I set the board to boot from "No Boot/JTAG DSP Little Endian Boot" mode. I am using CCS 5.5.0.00077 and the onboard XDS2xx USB emulator to connect to the board.

When I connect to the target, and read from the DEVSPEED register, I get 0. That means both the ARM and DSP cores work at 800MHz. Is this expected? I'd appreciate if you could confirm, or point out what I am missing. Thanks!

The target settings of my project are like this:

The target configuration is like this. You can see that there is no GEL file used to initialize the core. At least I didn't specify one:

over 9 years ago

0 Senthilkumar Srinivasan over 9 years ago

TI__Mastermind 43660 points

Hello Robby,

The DEVSPEED register should return this hex value: 0x00800002 for EVMK2H; which corresponds to 1.2 GHz for both C66 and ARM cores.

Regards,
Senthil

0 Ganapathi Dhandapani95 over 9 years ago

TI__Mastermind 28085 points

I think problem on your target configuration file. Better to install latest MCSDK3.0 package and select the K2H device target configuration file at below path.
MCSDK Path: \ti\mcsdk_bios_3_01_01_04\tools\program_evm\configs\evmk2h\evmk2h.ccxml

Thanks,

0 RobbySun over 9 years ago in reply to Ganapathi Dhandapani95

Expert 1120 points

Hmmm ... I used C:\TI\mcsdk_bios_3_01_01_04\tools\program_evm\configs\evmk2h\evmk2h.ccxml as suggested, also the file xtcievmk2x.gel it referred to. However, DEVSPEED is still 0, although I can load and run my code to finish. See the screen shot below:

0 RobbySun over 9 years ago in reply to RobbySun

Expert 1120 points

The GEL file seemed to run OK the first time when I connected to the target:

********************************************************************************
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: TCI6638K2K GEL file Ver is 1.3
C66xx_0: GEL Output: Detected PLL bypass enabled: SECCTL[BYPASS] = 0x00800000
C66xx_0: GEL Output: (2a) MAINPLLCTL1 = 0x00000040
C66xx_0: GEL Output: (2b) PLLCTL = 0x00000048
C66xx_0: GEL Output: (2c) PLLCTL = 0x00000048
C66xx_0: GEL Output: (2d) Delay...
C66xx_0: GEL Output: (2e) SECCTL = 0x00810000
C66xx_0: GEL Output: (2f) PLLCTL = 0x0000004A
C66xx_0: GEL Output: (2g) Delay...
C66xx_0: GEL Output: (2h) PLLCTL = 0x00000048
C66xx_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F
C66xx_0: GEL Output: MAINPLLCTL0 = 0x05000000
C66xx_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040
C66xx_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (7) SECCTL = 0x00890000
C66xx_0: GEL Output: (8a) Delay...
C66xx_0: GEL Output: PLL1_DIV3 = 0x00008002
C66xx_0: GEL Output: PLL1_DIV4 = 0x00008004
C66xx_0: GEL Output: PLL1_DIV7 = 0x00000000
C66xx_0: GEL Output: (8d/e) Delay...
C66xx_0: GEL Output: (10) Delay...
C66xx_0: GEL Output: (12) Delay...
C66xx_0: GEL Output: (13) SECCTL = 0x00090000
C66xx_0: GEL Output: (Delay...
C66xx_0: GEL Output: (Delay...
C66xx_0: GEL Output: (14) PLLCTL = 0x00000041
C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):
C66xx_0: GEL Output: PLL has been configured (122.88 MHz * 16 / 1 / 2 = 983.04 MHz)
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL.
C66xx_0: GEL Output: Completed PA PLL Setup
C66xx_0: GEL Output: PAPLLCTL0 - before: 0x0x098804C0 after: 0x0x07080400
C66xx_0: GEL Output: PAPLLCTL1 - before: 0x0x00000040 after: 0x0x00002040
C66xx_0: GEL Output: DDR begin
C66xx_0: GEL Output: XMC setup complete.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.
C66xx_0: GEL Output: DDR3A initialization complete
C66xx_0: GEL Output: DDR3 PLL Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3B clock now running at 800MHz.
C66xx_0: GEL Output: DDR3B initialization complete
C66xx_0: GEL Output: DDR done
********************************************************************************

Any idea why this is happening?