This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[DSP] How to run hyperlink example with RTM-BOC?

Other Parts Discussed in Thread: 66AK2H12

Hello E2E members and TI employees.

I have a question related to hyperlink test externally on two 66AK2H12 with RTM-BOC.

Test environment is as follows.

(1) target: two 66AK2H12 with RTM-BOC (refer to below picture)

(2) example project name: hyplnk_K2HC66BiosExampleProject

(3) test method: run 'hyplnk_K2HC66BiosExampleProject.out' each target on the dsp core0.

(4) console message: 

[C66xx_0] Version #: 0x02010001; string HYPLNK LLD Revision: 02.01.00.01:Oct 1 2014:23:55:00
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e902101
Status register contents:
Raw = 0x00003004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
Waiting for other side to come up ( 0)
Waiting for other side to come up ( 1)
Waiting for other side to come up ( 2)

...

I think that the example code is not suitable completely for keystone II devices, and that needs to modify some codes for this test.

If you have a comment to solve about that, please tell me how to solve it.

Thank you!

Gilbert Kim.

  • Hi Gilbert Kim,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please refer the links below my signature.

    I recommend you to go through the readme.txt (..\ti\pdk_keystone2_3_xx_xx_xx\packages\ti\drv\hyplnk\example\memoryMappedExample) for example usage.

    Thank you.

  • Hi,

    I think you have run the hyperlink example on single side DSP only. If you want to run Hyperlink example on board to board mode means you need to run the same .out file on both DSPs core0. Default TI MCSDK example supports hyperlink port 0, board to board mode. I have attached my test setup and log message for your reference.

    MCSDK_example_K2H_Hyperlink_port1.txt
    [C66xx_0] Version #: 0x02010001; string HYPLNK LLD Revision: 02.01.00.01:Oct  1 2014:23:55:00
    About to do system setup (PLL, PSC, and DDR)
    Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305
    system setup worked
    About to set up HyperLink Peripheral
    ============================Hyperlink Testing Port 1 
    ========================================== begin registers before initialization ===========
    Revision register contents:
      Raw    = 0x4e902101
    Status register contents:
      Raw        = 0x00003004
    Link status register contents:
      Raw       = 0x00000000
    Control register contents:
      Raw             = 0x00000000
    Control register contents:
      Raw        = 0x00000000
    ============== end registers before initialization ===========
    Waiting for other side to come up (       0)
    Waiting for other side to come up (       1)
    Version #: 0x02010001; string HYPLNK LLD Revision: 02.01.00.01:Oct  1 2014:23:55:00
    About to do system setup (PLL, PSC, and DDR)
    Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305
    system setup worked
    About to set up HyperLink Peripheral
    ============================Hyperlink Testing Port 1 
    ========================================== begin registers before initialization ===========
    Revision register contents:
      Raw    = 0x4e902101
    Status register contents:
      Raw        = 0x00003004
    Link status register contents:
      Raw       = 0x00000000
    Control register contents:
      Raw             = 0x00000000
    Control register contents:
      Raw        = 0x00000000
    ============== end registers before initialization ===========
    ============== begin registers after initialization ===========
    Status register contents:
      Raw        = 0x04402005
    Link status register contents:
      Raw       = 0xccf00cff
    Control register contents:
      Raw             = 0x00006204
    ============== end registers after initialization ===========
    Waiting 5 seconds to check link stability
    Waiting for other side to come up (       2)
    ============== begin registers after initialization ===========
    Status register contents:
      Raw        = 0x04402005
    Link status register contents:
      Raw       = 0xfdf0bdf0
    Control register contents:
      Raw             = 0x00006204
    ============== end registers after initialization ===========
    Waiting 5 seconds to check link stability
    Precursors 0 
    Postcursors: 19 
    Link seems stable
    About to try to read remote registers
    ============== begin REMOTE registers after initialization ===========
    Status register contents:
      Raw        = 0x0440200b
    Link status register contents:
      Raw       = 0xfdf0bdf0
    Control register contents:
      Raw             = 0x00006204
    ============== end REMOTE registers after initialization ===========
    Peripheral setup worked
    About to read/write once
    Precursors 0 
    Postcursors: 19 
    Link seems stable
    About to try to read remote registers
    ============== begin REMOTE registers after initialization ===========
    Status register contents:
      Raw        = 0x0440080f
    Link status register contents:
      Raw       = 0xfdf0bdf0
    Control register contents:
      Raw             = 0x00006200
    ============== end REMOTE registers after initialization ===========
    Peripheral setup worked
    About to read/write once
    Single write test passed
    About to pass 65536 tokens; iteration = 0
    Single write test passed
    About to pass 65536 tokens; iteration = 0
    === this is not an optimized example ===
    Link Speed is 4 * 6.25 Gbps
    Passed 65536 tokens round trip (read+write through hyplnk) in 17023 Mcycles
    Approximately 259751 cycles per round-trip
    === this is not an optimized example ===
    Checking statistics
    About to pass 65536 tokens; iteration = 1
    === this is not an optimized example ===
    Link Speed is 4 * 6.25 Gbps
    Passed 65536 tokens round trip (read+write through hyplnk) in 17023 Mcycles
    Approximately 259751 cycles per round-trip
    === this is not an optimized example ===
    Checking statistics
    About to pass 65536 tokens; iteration = 1
    === this is not an optimized example ===
    Link Speed is 4 * 6.25 Gbps
    Passed 65536 tokens round trip (read+write through hyplnk) in 17023 Mcycles
    Approximately 259751 cycles per round-trip
    === this is not an optimized example ===
    Checking statistics
    About to pass 65536 tokens; iteration = 2
    === this is not an optimized example ===
    Link Speed is 4 * 6.25 Gbps
    Passed 65536 tokens round trip (read+write through hyplnk) in 17023 Mcycles
    Approximately 259751 cycles per round-trip
    === this is not an optimized example ===
    Checking statistics
    About to pass 65536 tokens; iteration = 2
    === this is not an optimized example ===
    Link Speed is 4 * 6.25 Gbps
    Passed 65536 tokens round trip (read+write through hyplnk) in 17022 Mcycles
    Approximately 259750 cycles per round-trip
    === this is not an optimized example ===
    Checking statistics
    About to pass 65536 tokens; iteration = 3
    === this is not an optimized example ===
    Link Speed is 4 * 6.25 Gbps
    Passed 65536 tokens round trip (read+write through hyplnk) in 17022 Mcycles
    Approximately 259750 cycles per round-trip
    === this is not an optimized example ===
    Checking statistics
    About to pass 65536 tokens; iteration = 3
    === this is not an optimized example ===
    Link Speed is 4 * 6.25 Gbps
    Passed 65536 tokens round trip (read+write through hyplnk) in 17020 Mcycles
    Approximately 259713 cycles per round-trip
    === this is not an optimized example ===
    Checking statistics
    About to pass 65536 tokens; iteration = 4
    === this is not an optimized example ===
    Link Speed is 4 * 6.25 Gbps
    Passed 65536 tokens round trip (read+write through hyplnk) in 17020 Mcycles
    Approximately 259713 cycles per round-trip
    === this is not an optimized example ===
    Checking statistics
    About to pass 65536 tokens; iteration = 4
    

    Refer keystone lab manual, it should help you for run the hyperlink example.

    Thanks,

  • I solved this issue.
    Thank you!